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soc/intel/common/cse: Update comment for post-CAR global world 

Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Patrick Georgi 2019-12-02 11:43:20 +01:00
parent 5cdbce8072
commit 08c8cf9586
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/common/block/cse/cse.c
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@ -146,7 +146,7 @@ static uint32_t get_cse_bar(void)
static uint32_t read_bar(uint32_t offset)
{
/* Reach PCI config space to get BAR in case CAR global not available */
/* Load and cache BAR */
if (!cse.sec_bar)
cse.sec_bar = get_cse_bar();
return read32((void *)(cse.sec_bar + offset));
@ -154,7 +154,7 @@ static uint32_t read_bar(uint32_t offset)
static void write_bar(uint32_t offset, uint32_t val)
{
/* Reach PCI config space to get BAR in case CAR global not available */
/* Load and cache BAR */
if (!cse.sec_bar)
cse.sec_bar = get_cse_bar();
return write32((void *)(cse.sec_bar + offset), val);