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sb/amd/cimx/sb800: add C bootblock southbridge initialization 

TEST=boot PC Engines apu1 with C bootblock patch and launch
Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37329
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2019-11-28 14:14:52 +01:00 committed by Kyösti Mälkki
parent 8cee45c3f8
commit 08cd65198e
2 changed files with 23 additions and 4 deletions
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4
src/southbridge/amd/cimx/sb800/Makefile.inc
View File

@ -16,6 +16,10 @@
# SB800 Platform Files
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += bootblock.c
endif
romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c smbus_spd.c

23
src/southbridge/amd/cimx/sb800/bootblock.c
View File

@ -79,18 +79,21 @@ static void enable_spi_fast_mode(void)
pci_io_write_config32(dev, 0xa0, save);
}
static void enable_clocks(void)
static void enable_acpimmio_decode_pm24(void)
{
u8 reg8;
u32 reg32;
volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(reg8, 0xCD7);
}
static void enable_clocks(void)
{
u32 reg32;
volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program SB800 MiscClkCntrl register to configure clock output on the
// 14M_25M_48M_OSC ball usually used for the Super-I/O.
@ -112,5 +115,17 @@ static void bootblock_southbridge_init(void)
enable_rom();
enable_prefetch();
enable_spi_fast_mode();
// Program AcpiMmioEn to enable MMIO access to MiscCntrl register
enable_acpimmio_decode_pm24();
enable_clocks();
}
#if !CONFIG(ROMCC_BOOTBLOCK)
#include <bootblock_common.h>
void bootblock_soc_early_init(void)
{
bootblock_southbridge_init();
}
#endif