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mainboard/ocp/tiogapass: Set longer BMC timeout 

The BMC isn't always ready in 60 seconds if it printing debug output.
Give it 90 seconds to finish before timing out in coreboot.

Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
This commit is contained in:
Marc Jones 2020-11-06 10:45:38 -07:00 committed by Marc Jones
parent a575759c40
commit 092245dfbb
1 changed files with 1 additions and 1 deletions
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src/mainboard/ocp/tiogapass/devicetree.cb
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@ -74,7 +74,7 @@ chip soc/intel/xeon_sp/skx
chip drivers/ipmi # BMC KCS chip drivers/ipmi # BMC KCS
device pnp ca2.0 on end device pnp ca2.0 on end
register "bmc_i2c_address" = "0x20" register "bmc_i2c_address" = "0x20"
register "bmc_boot_timeout" = "60" register "bmc_boot_timeout" = "90"
end end
end # Intel Corporation C621 Series Chipset LPC/eSPI Controller end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller