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soc/intel/alderlake: Add TBT PCIe root ports enablement 

Ports are enabled according to devicetree.

BUG=none
TEST=Boot device, TBT should be functional

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Bernardo Perez Priego 2021-05-18 18:39:19 -07:00 committed by Tim Wawrzynczak
parent 193ee64d52
commit 095f97b58f
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/alderlake/fsp_params.c
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@ -251,6 +251,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
/* USB4/TBT */
for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++)
params->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i));
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);