Add support for E7505 northbridge.
Adapted from northbridge/intel/e7501 with only minor changes. This commit provides minimal patch from e7501 and I prefer any cosmetic clean-up to be done after initial merge. Due the incomplete register specifications, it is safer to have e7505 as a separate directory in case I improve it to support wider range of memory configurations. I have no e7501 to test with. Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/295 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
Stefan Reinauer
parent
20fc631ad2
commit
0a0d5e8b86
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@ -1,4 +1,5 @@
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source src/northbridge/intel/e7501/Kconfig
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source src/northbridge/intel/e7505/Kconfig
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source src/northbridge/intel/e7520/Kconfig
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source src/northbridge/intel/e7525/Kconfig
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source src/northbridge/intel/i3100/Kconfig
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@ -1,4 +1,5 @@
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100
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@ -1,4 +1,4 @@
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config NORTHBRIDGE_INTEL_E7501
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config NORTHBRIDGE_INTEL_E7505
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bool
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select HAVE_DEBUG_RAM_SETUP
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@ -1,5 +1,6 @@
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struct northbridge_intel_e7501_config
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struct northbridge_intel_e7505_config
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{
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};
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extern struct chip_operations northbridge_intel_e7501_ops;
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extern struct chip_operations northbridge_intel_e7505_ops;
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@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev)
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for(i = 0; i < 256; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\n%02x:",i);
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#else
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print_debug("\n");
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@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev)
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#endif
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}
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val = pci_read_config8(dev, i);
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, " %02x", val);
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#else
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print_debug_char(' ');
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@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
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device = ctrl->channel0[i];
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if (device) {
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int j;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
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#else
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print_debug("dimm: ");
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@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\n%02x: ", j);
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#else
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print_debug("\n");
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@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
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break;
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}
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byte = status & 0xff;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "%02x ", byte);
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#else
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print_debug_hex8(byte);
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@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
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device = ctrl->channel1[i];
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if (device) {
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int j;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
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#else
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print_debug("dimm: ");
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@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\n%02x: ", j);
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#else
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print_debug("\n");
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@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
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break;
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}
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byte = status & 0xff;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "%02x ", byte);
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#else
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print_debug_hex8(byte);
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@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void)
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for(device = 1; device < 0x80; device++) {
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int j;
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if( smbus_read_byte(device, 0) < 0 ) continue;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "smbus: %02x", device);
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#else
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print_debug("smbus: ");
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@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void)
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break;
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}
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if ((j & 0xf) == 0) {
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\n%02x: ",j);
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#else
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print_debug("\n");
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@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void)
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#endif
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}
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byte = status & 0xff;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "%02x ", byte);
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#else
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print_debug_hex8(byte);
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@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port)
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{
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int i;
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "%04x:\n", port);
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#else
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print_debug_hex16(port);
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@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port)
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for(i=0;i<256;i++) {
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uint8_t val;
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if ((i & 0x0f) == 0) {
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "%02x:", i);
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#else
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print_debug_hex8(i);
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@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port)
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#endif
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}
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val = inb(port);
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, " %02x",val);
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#else
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print_debug_char(' ');
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@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end)
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print_debug("dump_mem:");
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for(i=start;i<end;i++) {
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if((i & 0xf)==0) {
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\n%08x:", i);
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#else
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print_debug("\n");
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@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end)
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print_debug(":");
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#endif
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}
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#if CONFIG_CACHE_AS_RAM
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
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#else
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print_debug(" ");
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@ -19,7 +19,7 @@
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*/
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/*
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* e7501.h: PCI configuration space for the Intel E7501 memory controller
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* e7505.h: PCI configuration space for the Intel E7501 memory controller
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*/
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/************ D0:F0 ************/
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@ -8,6 +8,7 @@
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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#include "e7505.h"
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#if CONFIG_WRITE_HIGH_TABLES==1
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#include <cbmem.h>
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@ -65,17 +66,17 @@ static void pci_domain_set_resources(device_t dev)
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/* Write the ram configuration registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, 0xc4);
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tolm_r = pci_read_config16(mc_dev, TOLM);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, 0xc4, tolm_r);
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pci_write_config16(mc_dev, TOLM, tolm_r);
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remapbase_r = pci_read_config16(mc_dev, 0xc6);
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remapbase_r = pci_read_config16(mc_dev, REMAPBASE);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc6, remapbase_r);
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pci_write_config16(mc_dev, REMAPBASE, remapbase_r);
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remaplimit_r = pci_read_config16(mc_dev, 0xc8);
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remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc8, remaplimit_r);
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pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r);
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/* Report the memory regions */
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idx = 10;
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@ -98,12 +99,23 @@ static void pci_domain_set_resources(device_t dev)
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assign_resources(dev->link_list);
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}
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static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations intel_pci_ops = {
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.set_subsystem = intel_set_subsystem,
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};
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci = &intel_pci_ops,
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.ops_pci_bus = &pci_cf8_conf1,
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};
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@ -135,7 +147,8 @@ static void enable_dev(struct device *dev)
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}
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}
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struct chip_operations northbridge_intel_e7501_ops = {
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CHIP_NAME("Intel E7501 Northbridge")
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struct chip_operations northbridge_intel_e7505_ops = {
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CHIP_NAME("Intel E7505 Northbridge")
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.enable_dev = enable_dev,
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};
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@ -15,7 +15,7 @@
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#include <spd.h>
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#include <sdram_mode.h>
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#include <stdlib.h>
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#include "e7501.h"
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#include "e7505.h"
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/*-----------------------------------------------------------------------------
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Definitions:
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@ -176,7 +176,8 @@ static const long constant_register_values[] = {
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// without jumping through 36-bit adddressing hoops, even if the
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// total memory is > 4 GB. Changing these values may break do_ram_command()!
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0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
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0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
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// 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
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0x64, 0x00000000, (0x04 << 0) | (0x04 << 8) | (0x04 << 16) | (0x04 << 24),
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/* DRA - DRAM Row Attribute Register
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* 0x70 Row 0,1
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@ -260,7 +261,8 @@ static const long constant_register_values[] = {
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// The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
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// Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
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0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16),
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// 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16),
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0x78, 0xC7F8FFFF, (0x03<<16)|(0x28<<24),
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/* FIXME why was I attempting to set a reserved bit? */
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/* 0x0100040f */
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@ -314,7 +316,8 @@ static const long constant_register_values[] = {
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// Default to dual-channel mode, ECC, 1-clock address/cmd hold
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// NOTE: configure_e7501_dram_controller_mode() configures further
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0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8),
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// 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8),
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0x7c, 0xffcef8f7, 0x00210008,
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/* Another Intel undocumented register
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* 0x88 - 0x8B
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@ -400,7 +403,8 @@ static const long constant_register_values[] = {
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*/
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// Enable D0:D1, disable D2:F1, D3:F1, D4:F1
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0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0),
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// 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0),
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0xe0, 0xfffffffa, 0x0,
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// Undocumented
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0xd8, 0xffff9fff, 0x00000000,
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@ -422,7 +426,7 @@ static const long constant_register_values[] = {
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* [00:00] Unknown - not used?
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*/
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0xf4, 0x3f8ffffd, 0x40300002,
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// 0xf4, 0x3f8ffffd, 0x40300002,
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#ifdef SUSPICIOUS_LOOKING_CODE
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// SJM: Undocumented.
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@ -432,12 +436,13 @@ static const long constant_register_values[] = {
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};
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/* DDR RECOMP tables */
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#if 0
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// Slew table for 1x drive?
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static const uint32_t maybe_1x_slew_table[] = {
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0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
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0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
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};
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#endif
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// Slew table for 2x drive?
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static const uint32_t maybe_2x_slew_table[] = {
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@ -478,16 +483,64 @@ static void do_delay(void)
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#define EXTRA_DELAY DO_DELAY
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static void die_on_spd_error(int spd_return_value)
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/*-----------------------------------------------------------------------------
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Handle (undocumented) control bits in device 0:6.0
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-----------------------------------------------------------------------------*/
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/**
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*
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*/
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static void ram_handle_d060_1(void)
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{
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if (spd_return_value < 0)
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die("Error reading SPD info\n");
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uint32_t dword;
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dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
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dword |= 0x02;
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pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
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dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0);
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dword |= 0x04;
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pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword);
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dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
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dword &= ~0x02;
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pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
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}
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||||
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/**
|
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*
|
||||
*/
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static void ram_handle_d060_2(void)
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||||
{
|
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uint32_t dword;
|
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uint8_t revision;
|
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revision = pci_read_config8(PCI_DEV(0,0,0), 0x08);
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if (revision >= 3) {
|
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dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
|
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dword |= 0x02;
|
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pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
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||||
|
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dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0);
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dword |= 0x18000000;
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pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword);
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||||
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dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
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dword &= ~0x02;
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pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
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||||
}
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||||
}
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||||
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||||
/*-----------------------------------------------------------------------------
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Serial presence detect (SPD) functions:
|
||||
-----------------------------------------------------------------------------*/
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||||
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||||
static void die_on_spd_error(int spd_return_value)
|
||||
{
|
||||
if (spd_return_value < 0)
|
||||
die("Error reading SPD info\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the page size for each physical bank of the DIMM:
|
||||
* log2(page size) = (# columns) + log2(data width)
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||||
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|
@ -843,10 +896,10 @@ SDRAM configuration functions:
|
|||
*/
|
||||
static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
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||||
{
|
||||
int i;
|
||||
uint8_t dimm_start_64M_multiple;
|
||||
uint32_t dimm_start_address;
|
||||
uint32_t dram_controller_mode;
|
||||
uint8_t dimm_start_64M_multiple = 0;
|
||||
uint16_t e7501_mode_bits = jedec_mode_bits;
|
||||
uint8_t i;
|
||||
|
||||
// Configure the RAM command
|
||||
dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
|
||||
|
|
@ -856,58 +909,43 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
|
|||
|
||||
// RAM_COMMAND_NORMAL is an exception.
|
||||
// It affects only the memory controller and does not need to be "sent" to the DIMMs.
|
||||
if (command == RAM_COMMAND_NORMAL)
|
||||
return;
|
||||
|
||||
if (command != RAM_COMMAND_NORMAL) {
|
||||
// NOTE: for mode select commands, some of the location address bits are part of the command
|
||||
// Map JEDEC mode bits to E7505
|
||||
if (command == RAM_COMMAND_MRS) {
|
||||
// Host address lines [25:18] map to DIMM address lines [7:0]
|
||||
// Host address lines [17:16] map to DIMM address lines [9:8]
|
||||
// Host address lines [15:4] map to DIMM address lines [11:0]
|
||||
dimm_start_address = (jedec_mode_bits & 0x00ff) << 18;
|
||||
dimm_start_address |= (jedec_mode_bits & 0x0300) << 8;
|
||||
dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4;
|
||||
} else if (command == RAM_COMMAND_EMRS) {
|
||||
// Host address lines [15:4] map to DIMM address lines [11:0]
|
||||
dimm_start_address = (jedec_mode_bits << 4);
|
||||
} else {
|
||||
ASSERT(jedec_mode_bits == 0);
|
||||
dimm_start_address = 0;
|
||||
}
|
||||
|
||||
// Send the command to all DIMMs by accessing a memory location within each
|
||||
// NOTE: for mode select commands, some of the location address bits
|
||||
// are part of the command
|
||||
// Send the command to all DIMMs by accessing a memory location within each
|
||||
|
||||
// Map JEDEC mode bits to E7501
|
||||
if (command == RAM_COMMAND_MRS) {
|
||||
// Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
|
||||
// The E7501 hard-sets DIMM address lines 10 & 0 to zero
|
||||
dimm_start_64M_multiple = 0;
|
||||
|
||||
ASSERT(!(jedec_mode_bits & 0x0401));
|
||||
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
|
||||
|
||||
e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15
|
||||
((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13
|
||||
|
||||
} else if (command == RAM_COMMAND_EMRS) {
|
||||
// Host address lines [15:3] map to DIMM address lines [12:0]
|
||||
e7501_mode_bits = jedec_mode_bits <<= 3;
|
||||
} else
|
||||
ASSERT(jedec_mode_bits == 0);
|
||||
|
||||
dimm_start_64M_multiple = 0;
|
||||
|
||||
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
|
||||
|
||||
uint8_t dimm_end_64M_multiple =
|
||||
pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
|
||||
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
|
||||
|
||||
// This code assumes DRAM row boundaries are all set below 4 GB
|
||||
// NOTE: 0x40 * 64 MB == 4 GB
|
||||
ASSERT(dimm_start_64M_multiple < 0x40);
|
||||
|
||||
// NOTE: 2^26 == 64 MB
|
||||
|
||||
uint32_t dimm_start_address =
|
||||
dimm_start_64M_multiple << 26;
|
||||
|
||||
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
|
||||
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
|
||||
RAM_DEBUG_MESSAGE("\n");
|
||||
|
||||
read32(dimm_start_address + e7501_mode_bits);
|
||||
uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
|
||||
|
||||
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
|
||||
dimm_start_address &= 0x3ffffff;
|
||||
dimm_start_address |= dimm_start_64M_multiple << 26;
|
||||
read32(dimm_start_address);
|
||||
// Set the start of the next DIMM
|
||||
dimm_start_64M_multiple =
|
||||
dimm_end_64M_multiple;
|
||||
}
|
||||
dimm_start_64M_multiple = dimm_end_64M_multiple;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1136,13 +1174,10 @@ static void initialize_ecc(void)
|
|||
dram_controller_mode >>= 20;
|
||||
dram_controller_mode &= 3;
|
||||
if (dram_controller_mode == 2) {
|
||||
|
||||
uint8_t byte;
|
||||
|
||||
RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
|
||||
/* Initialize ECC bits , use ECC zero mode (new to 7501) */
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x01);
|
||||
|
||||
// Wait for scrub cycle to complete
|
||||
do {
|
||||
|
|
@ -1150,7 +1185,7 @@ static void initialize_ecc(void)
|
|||
pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
|
||||
} while ((byte & 0x08) == 0);
|
||||
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, (byte & 0xfc) | 0x04);
|
||||
RAM_DEBUG_MESSAGE("ECC state initialized.\n");
|
||||
|
||||
/* Clear the ECC error bits */
|
||||
|
|
@ -1160,9 +1195,6 @@ static void initialize_ecc(void)
|
|||
// Clear DRAM Interface error bits (write-one-clear)
|
||||
pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18);
|
||||
pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18);
|
||||
|
||||
// Start normal ECC scrub
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -1403,11 +1435,11 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
|
|||
|
||||
maybe_dram_read_timing =
|
||||
pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
|
||||
maybe_dram_read_timing &= 0xF00C;
|
||||
maybe_dram_read_timing &= 0xF000;
|
||||
|
||||
if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
|
||||
dram_timing |= DRT_CAS_2_0;
|
||||
maybe_dram_read_timing |= 0xBB1;
|
||||
maybe_dram_read_timing |= 0x0222;
|
||||
} else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
|
||||
|
||||
uint32_t dram_row_attributes =
|
||||
|
|
@ -1438,22 +1470,22 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
|
|||
dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
|
||||
dword |= (1 << 26);
|
||||
pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
|
||||
|
||||
dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */
|
||||
dword |= 0xd2109800;
|
||||
|
||||
/* patch try register 88 is undocumented tnz */
|
||||
dword &= 0x0ca17fff;
|
||||
dword |= 0xd14a5000;
|
||||
pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
|
||||
|
||||
pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
|
||||
maybe_dram_read_timing);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */
|
||||
/* clear master DLL reset */
|
||||
dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
|
||||
dword &= ~(1 << 26);
|
||||
pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
|
||||
|
||||
return;
|
||||
|
||||
hw_err:
|
||||
hw_err:
|
||||
die(SPD_ERROR);
|
||||
}
|
||||
|
||||
|
|
@ -1627,6 +1659,8 @@ static void enable_e7501_clocks(uint8_t dimm_mask)
|
|||
int i;
|
||||
uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
|
||||
|
||||
pci_write_config8(PCI_DEV(0,0,0), 0x8e, 0xb0);
|
||||
|
||||
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
|
||||
|
||||
uint8_t socket_mask = 1 << i;
|
||||
|
|
@ -1727,7 +1761,7 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
|
|||
static void ram_set_rcomp_regs(void)
|
||||
{
|
||||
uint32_t dword;
|
||||
uint8_t maybe_strength_control;
|
||||
uint8_t maybe_strength_control, revision;
|
||||
|
||||
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
|
||||
|
||||
|
|
@ -1745,81 +1779,105 @@ static void ram_set_rcomp_regs(void)
|
|||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
|
||||
/* Begin to write the RCOMP registers */
|
||||
write8(RCOMP_MMIO + 0x2c, 0x0);
|
||||
|
||||
// Set CMD and DQ/DQS strength to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
|
||||
maybe_strength_control |= 0x44;
|
||||
maybe_strength_control |= 0x40;
|
||||
write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
|
||||
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
|
||||
write16(RCOMP_MMIO + 0x42, 0);
|
||||
|
||||
write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
|
||||
|
||||
// NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
|
||||
// Set CMD and DQ/DQS strength to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0xF8;
|
||||
maybe_strength_control |= 0x04;
|
||||
write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x60);
|
||||
write16(RCOMP_MMIO + 0x40, 0);
|
||||
|
||||
// Set RCVEnOut# strength to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
|
||||
maybe_strength_control |= 4;
|
||||
maybe_strength_control |= 0x04;
|
||||
write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
|
||||
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
|
||||
write16(RCOMP_MMIO + 0x50, 0);
|
||||
|
||||
// Set CS# strength for x4 SDRAM to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
|
||||
maybe_strength_control |= 4;
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x88;
|
||||
maybe_strength_control |= 0x04;
|
||||
write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
|
||||
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
|
||||
write16(RCOMP_MMIO + 0x48, 0);
|
||||
|
||||
// Set CKE strength for x4 SDRAM to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
|
||||
maybe_strength_control |= 4;
|
||||
write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
|
||||
// Set CS# strength for x4 SDRAM to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x8F;
|
||||
maybe_strength_control |= 0x40;
|
||||
write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x160);
|
||||
write16(RCOMP_MMIO + 0x4a, 0);
|
||||
|
||||
// Set CKE strength for x4 SDRAM to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x88;
|
||||
maybe_strength_control |= 0x04;
|
||||
write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
|
||||
write16(RCOMP_MMIO + 0x44, 0);
|
||||
|
||||
// Set CK strength for x4 SDRAM to 1x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
|
||||
maybe_strength_control |= 1;
|
||||
write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
|
||||
// Set CKE strength for x4 SDRAM to 2x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x8F;
|
||||
maybe_strength_control |= 0x40;
|
||||
write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
|
||||
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xc0);
|
||||
write16(RCOMP_MMIO + 0x46, 0);
|
||||
|
||||
// Set CK strength for x4 SDRAM to 1x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x88;
|
||||
maybe_strength_control |= 0x01;
|
||||
write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
|
||||
write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
|
||||
write16(RCOMP_MMIO + 0x4c, 0);
|
||||
|
||||
write8(RCOMP_MMIO + 0x2c, 0xff);
|
||||
// Set CK strength for x4 SDRAM to 1x (?)
|
||||
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x8F;
|
||||
maybe_strength_control |= 0x10;
|
||||
write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
|
||||
write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
|
||||
write16(RCOMP_MMIO + 0x4e, 0);
|
||||
|
||||
// Set the digital filter length to 8 (?)
|
||||
|
||||
dword = read32(RCOMP_MMIO + 0x400);
|
||||
dword &= 0x7f7fffff;
|
||||
write32(RCOMP_MMIO + 0x400, dword);
|
||||
|
||||
dword = read32(RCOMP_MMIO + 0x408);
|
||||
dword &= 0x7f7fffff;
|
||||
write32(RCOMP_MMIO + 0x408, dword);
|
||||
|
||||
ram_handle_d060_1();
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST);
|
||||
dword &= 0x3fffffff;
|
||||
pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword);
|
||||
|
||||
revision = pci_read_config8(PCI_DEV(0,0,0), 0x08);
|
||||
if (revision >= 3) {
|
||||
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
|
||||
dword &= ~0x100;
|
||||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
|
||||
dword |= 0x500;
|
||||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
}
|
||||
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
|
||||
|
||||
// NOTE: Some factory BIOS don't do this.
|
||||
// Doesn't seem to matter either way.
|
||||
dword &= ~2;
|
||||
|
||||
dword |= 1;
|
||||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
|
||||
/* Wait 40 usec */
|
||||
SLOW_DOWN_IO;
|
||||
|
||||
/* unblock updates */
|
||||
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
|
||||
dword &= ~(1 << 9);
|
||||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
|
||||
// Force a RCOMP measurement cycle?
|
||||
dword |= (1 << 8);
|
||||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
dword &= ~(1 << 8);
|
||||
dword &= ~0x203;
|
||||
dword |= 0x401;
|
||||
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
|
||||
|
||||
/* Wait 40 usec */
|
||||
SLOW_DOWN_IO;
|
||||
|
||||
// Clear the RCOMP MMIO base address
|
||||
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, 0);
|
||||
/*disable access to the rcomp bar */
|
||||
dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
|
||||
dword &= ~(1 << 22);
|
||||
|
|
@ -2004,4 +2062,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
|
||||
ram_set_rcomp_regs();
|
||||
ram_set_d0f0_regs();
|
||||
ram_handle_d060_2();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue