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mb/google/kohaku: Update TCC offset setting 

This change sets TCC offset to 10 for kohaku.

BUG=b:144532818
BRANCH=firmware-hatch-12672.B
TEST=Checked thermal and performance efficiency internally (b:144532818)

Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Grace Kao <grace.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Seunghwan Kim 2019-12-09 11:12:08 +09:00 committed by Patrick Georgi
parent 13746076e9
commit 0a2de7b538
1 changed files with 0 additions and 2 deletions
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src/mainboard/google/hatch/variants/kohaku/overridetree.cb
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@ -2,8 +2,6 @@ chip soc/intel/cannonlake
register "tdp_pl1_override" = "8" register "tdp_pl1_override" = "8"
register "tdp_pl2_override" = "51" register "tdp_pl2_override" = "51"
register "tcc_offset" = "35" # TCC of 65C
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,