drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support

FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown.  Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brenton Dong 2016-10-18 11:35:15 -07:00 committed by Martin Roth
parent f7acdf82cb
commit 0a5971c91b
8 changed files with 85 additions and 0 deletions

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@ -18,9 +18,14 @@
#include <main_decl.h>
#include <program_loading.h>
#include <soc/intel/common/util.h>
#include <fsp/util.h>
void main(void)
{
/* Call TempRamExit FSP API if enabled. */
if (IS_ENABLED(CONFIG_FSP_CAR))
fsp_temp_ram_exit();
console_init();
/* Recover cbmem so infrastruture using it is functional. */

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@ -53,6 +53,11 @@ config DISPLAY_UPD_DATA
Display the user specified product data prior to memory
initialization.
config FSP_T_CBFS
string "Name of FSP-T in CBFS"
depends on FSP_CAR
default "fspt.bin"
config FSP_S_CBFS
string "Name of FSP-S in CBFS"
default "fsps.bin"
@ -61,6 +66,12 @@ config FSP_M_CBFS
string "Name of FSP-M in CBFS"
default "fspm.bin"
config FSP_T_FILE
string "Intel FSP-T (temp ram init) binary path and filename"
depends on FSP_CAR
help
The path and filename of the Intel FSP-M binary for this platform.
config FSP_M_FILE
string "Intel FSP-M (memory init) binary path and filename"
depends on ADD_FSP_BINARIES
@ -73,6 +84,13 @@ config FSP_S_FILE
help
The path and filename of the Intel FSP-S binary for this platform.
config FSP_CAR
bool "Use FSP TempRamInit & TempRamExit APIs"
depends on ADD_FSP_BINARIES
default n
help
Use FSP APIs to initialize & Tear Down the Cache-As-Ram
config FSP_M_XIP
bool "Is FSP-M XIP"
default n

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@ -40,11 +40,18 @@ ramstage-y += util.c
ramstage-$(CONFIG_MMA) += mma_core.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
postcar-$(CONFIG_FSP_CAR) += util.c
postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
# Add FSP blobs into cbfs. SoC code may supply additional options with
# -options, e.g --xip or -b
cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS)
$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))
$(CONFIG_FSP_T_CBFS)-type := fsp
cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
$(CONFIG_FSP_M_CBFS)-type := fsp

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@ -40,6 +40,7 @@ enum fsp_notify_phase {
/* Main FSP stages */
void fsp_memory_init(bool s3wake);
void fsp_silicon_init(bool s3wake);
void fsp_temp_ram_exit(void);
/* Callbacks for updating stage-specific parameters */
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);

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@ -34,6 +34,8 @@ struct fsp_header {
uint16_t component_attribute;
size_t cfg_region_offset;
size_t cfg_region_size;
size_t temp_ram_init_entry;
size_t temp_ram_exit_entry;
size_t notify_phase_entry_offset;
size_t memory_init_entry_offset;
size_t silicon_init_entry_offset;

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@ -101,6 +101,7 @@ void fsp_handle_reset(uint32_t status);
/* SoC/chipset must provide this to handle platform-specific reset codes */
void chipset_handle_reset(uint32_t status);
typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param);
typedef asmlinkage uint32_t (*fsp_memory_init_fn)
(void *raminit_upd, void **hob_list);
typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd);

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@ -0,0 +1,49 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <arch/io.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <memrange.h>
#include <string.h>
#include <timestamp.h>
#include <cbfs.h>
void fsp_temp_ram_exit(void)
{
struct fsp_header hdr;
uint32_t status;
temp_ram_exit_fn temp_ram_exit;
struct cbfsf file_desc;
struct region_device file_data;
const char *name = CONFIG_FSP_M_CBFS;
if (cbfs_boot_locate(&file_desc, name, NULL)) {
printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name);
die("FSPM not available for CAR Exit!\n");
}
cbfs_file_data(&file_data, &file_desc);
if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS)
die("Invalid FSPM header!\n");
temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry);
printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", temp_ram_exit);
status = temp_ram_exit(NULL);
if (status != FSP_SUCCESS) {
printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status);
die("TempRamExit returned an error!\n");
}
}

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@ -52,6 +52,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
hdr->component_attribute = read16(raw_hdr + 34);
hdr->cfg_region_offset = read32(raw_hdr + 36);
hdr->cfg_region_size = read32(raw_hdr + 40);
hdr->temp_ram_init_entry = read32(raw_hdr + 48);
hdr->temp_ram_exit_entry = read32(raw_hdr + 64);
hdr->notify_phase_entry_offset = read32(raw_hdr + 56);
hdr->memory_init_entry_offset = read32(raw_hdr + 60);
hdr->silicon_init_entry_offset = read32(raw_hdr + 68);