soc/intel/alderlake: Add Raptor Lake device IDs
Add system agent ID for RPL QDF# Q271 TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is gone Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -4133,6 +4133,7 @@
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#define PCI_DID_INTEL_RPL_P_ID_1 0xa706
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#define PCI_DID_INTEL_RPL_P_ID_1 0xa706
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#define PCI_DID_INTEL_RPL_P_ID_2 0xa707
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#define PCI_DID_INTEL_RPL_P_ID_2 0xa707
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#define PCI_DID_INTEL_RPL_P_ID_3 0xa708
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#define PCI_DID_INTEL_RPL_P_ID_3 0xa708
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#define PCI_DID_INTEL_RPL_P_ID_4 0xa71b
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/* Intel SMBUS device Ids */
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/* Intel SMBUS device Ids */
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#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
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#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
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@ -74,6 +74,7 @@ static struct {
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{ PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" },
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{ PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" },
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{ PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" },
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{ PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" },
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{ PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" },
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{ PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" },
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{ PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-P" },
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};
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};
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@ -115,6 +115,7 @@ static const struct {
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{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W },
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{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W },
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{ PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },
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{ PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },
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{ PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
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{ PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
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{ PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W },
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};
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};
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/* Types of display ports */
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/* Types of display ports */
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@ -249,6 +249,7 @@ enum adl_cpu_type get_adl_cpu_type(void)
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PCI_DID_INTEL_RPL_P_ID_1,
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PCI_DID_INTEL_RPL_P_ID_1,
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PCI_DID_INTEL_RPL_P_ID_2,
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PCI_DID_INTEL_RPL_P_ID_2,
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PCI_DID_INTEL_RPL_P_ID_3,
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PCI_DID_INTEL_RPL_P_ID_3,
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PCI_DID_INTEL_RPL_P_ID_4,
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};
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};
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const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
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const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
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@ -517,6 +517,7 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
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case PCI_DID_INTEL_RPL_P_ID_1:
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case PCI_DID_INTEL_RPL_P_ID_1:
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case PCI_DID_INTEL_RPL_P_ID_2:
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case PCI_DID_INTEL_RPL_P_ID_2:
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case PCI_DID_INTEL_RPL_P_ID_3:
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case PCI_DID_INTEL_RPL_P_ID_3:
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case PCI_DID_INTEL_RPL_P_ID_4:
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tdp = get_cpu_tdp();
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tdp = get_cpu_tdp();
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if (tdp == TDP_45W)
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if (tdp == TDP_45W)
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return ICC_MAX_TDP_45W;
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return ICC_MAX_TDP_45W;
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@ -129,6 +129,7 @@ static const struct vr_lookup vr_config_ll[] = {
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
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{ PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
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@ -165,6 +166,7 @@ static const struct vr_lookup vr_config_icc[] = {
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
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{ PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) },
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@ -201,6 +203,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
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@ -237,6 +240,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
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{ PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
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{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
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@ -438,6 +438,7 @@ static const unsigned short systemagent_ids[] = {
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PCI_DID_INTEL_RPL_P_ID_1,
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PCI_DID_INTEL_RPL_P_ID_1,
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PCI_DID_INTEL_RPL_P_ID_2,
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PCI_DID_INTEL_RPL_P_ID_2,
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PCI_DID_INTEL_RPL_P_ID_3,
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PCI_DID_INTEL_RPL_P_ID_3,
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PCI_DID_INTEL_RPL_P_ID_4,
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0
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0
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};
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};
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