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mb/google/brask: Update PCH power cycle related durations 

The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.

BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.

Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Zhuohao Lee 2022-02-23 15:22:19 +08:00 committed by Felix Held
parent 09f3b6cf21
commit 0b108a14c0
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
View File

@ -61,6 +61,12 @@ chip soc/intel/alderlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
# HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"