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Zhuohao Lee 0b108a14c0 mb/google/brask: Update PCH power cycle related durations
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.

BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.

Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:46:19 +00:00
3rdparty Update blobs submodule to upstream master 2022-02-15 17:03:11 +00:00
Documentation Documentation/security/vboot: Update 4.16 vboot supported boards 2022-02-25 18:01:31 +00:00
LICENSES
configs src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard 2022-02-11 20:14:55 +00:00
payloads payloads/tianocore: Convert BMP at build time 2022-02-25 20:45:02 +00:00
spd spd/lp4x: Generate initial SPD for MT53E2G32D4NQ-046 WT:C 2022-02-24 00:31:25 +00:00
src mb/google/brask: Update PCH power cycle related durations 2022-02-25 20:46:19 +00:00
tests tests/include: Move EMPTY_WRAP() macro to tests/include/test.h 2022-02-10 21:16:49 +00:00
util crossgcc: Upgrade LLVM/clang from 12.0.0 to 13.0.1 2022-02-25 00:44:10 +00:00
.checkpatch.conf
.clang-format
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MAINTAINERS MAINTAINERS: Add myself 2022-02-18 19:57:44 +00:00
Makefile Makefile: Defer normalizing configuration for reproducible builds 2022-01-14 00:30:04 +00:00
Makefile.inc IASL: Ignore IASL's "Missing dependency" warning 2022-01-28 16:34:23 +00:00
README.md
gnat.adc
toolchain.inc

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.