hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
Change-Id: I181da410490a92760ae1328a4286e805f5388886 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5462 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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Alexandru Gagniuc
parent
05ba1bb6d4
commit
0b2fa34d31
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@ -368,72 +368,14 @@ GPIO_CONTROL parmer_gpio[] = {
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*/
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*/
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/*
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* information to AGESA
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* (e.g. MemClk routing, the number of DIMM slots per channel,...).
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* use its default conservative settings.
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* If PlatformSpecificTable is populated, AGESA will base its settings on the
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* data from the table. Otherwise, it will use its default conservative settings
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*/
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*/
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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//
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// The following macros are supported (use comma to separate macros):
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//
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// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
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// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
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// AGESA will base on this value to disable unused MemClk to save power.
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// Example:
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// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
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// Bit AM3/S1g3 pin name
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// 0 M[B,A]_CLK_H/L[0]
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// 1 M[B,A]_CLK_H/L[1]
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// 2 M[B,A]_CLK_H/L[2]
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// 3 M[B,A]_CLK_H/L[3]
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// 4 M[B,A]_CLK_H/L[4]
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// 5 M[B,A]_CLK_H/L[5]
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// 6 M[B,A]_CLK_H/L[6]
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// 7 M[B,A]_CLK_H/L[7]
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// And platform has the following routing:
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// CS0 M[B,A]_CLK_H/L[4]
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// CS1 M[B,A]_CLK_H/L[2]
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// CS2 M[B,A]_CLK_H/L[3]
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// CS3 M[B,A]_CLK_H/L[5]
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// Then platform can specify the following macro:
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// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
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//
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// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
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// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
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// AGESA will base on this value to tristate unused CKE to save power.
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//
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// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
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// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
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// AGESA will base on this value to tristate unused ODT pins to save power.
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//
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// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
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// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
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// AGESA will base on this value to tristate unused Chip select to save power.
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//
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// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
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// Specifies the number of DIMM slots per channel.
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//
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// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
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// Specifies the number of Chip selects per channel.
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//
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// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
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// Specifies the number of channels per socket.
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//
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// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
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// Specifies DDR bus speed of channel ChannelID on socket SocketID.
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//
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// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
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// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
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//
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// WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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// Byte6Seed, Byte7Seed, ByteEccSeed)
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// Specifies the write leveling seed for a channel of a socket.
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//
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// HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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// Byte6Seed, Byte7Seed, ByteEccSeed)
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// Speicifes the HW RXEN training seed for a channel of a socket
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//
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
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MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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@ -447,44 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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// Customer table
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// Customer table
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UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
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UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
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{
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{
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// Hardcoded Memory Training Values
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// The following macro should be used to override training values for your platform
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//
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
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//
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// NOTE:
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// The following training hardcode values are example values that were taken from a tilapia motherboard
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// with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
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// the table and replace the byte lane values with your own.
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//
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// ------------------ BYTE LANES ----------------------
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// BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
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// Write Data Timing
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// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
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// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
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// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
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// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
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// DQS Receiver Enable
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// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
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// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
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// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
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// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
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// Write DQS Delays
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
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// Read DQS Delays
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
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// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
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//--------------------------------------------------------------------------------------------------------------------------------------------------
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// TABLE END
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NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
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NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
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};
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};
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UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);
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UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);
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