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mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports 

Latency Tolerance Reporting is yet another PCIe power management feature
which can have a bad influence on realtime performance. Disable this
feature for all PCIe root ports.

Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Werner Zeh 2021-07-23 13:09:41 +02:00 committed by Patrick Georgi
parent cf35fd3748
commit 0b39a5a23a
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@ -77,6 +77,14 @@ chip soc/intel/elkhartlake
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[4]" = "true"
register "PcieRpLtrDisable[5]" = "true"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"