GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/picasso: Reduce 48M out configuration 

Picasso has only a single 48M output.  Simplify the setup function.
Note that while the feature is similar to older products, the register
definition and Enable bit has changed.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-06-20 11:03:06 -06:00 committed by Martin Roth
parent ad1fdac987
commit 0bd0806d2f
2 changed files with 4 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/amd/picasso/include/soc/southbridge.h
View File

@ -175,6 +175,7 @@
#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
#define MISC_CLK_CNTL1 0x40
#define CG1PLL_FBDIV_TEST BIT(26)
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
@ -312,7 +313,7 @@ struct soc_power_reg {
};
void enable_aoac_devices(void);
void sb_clk_output_48Mhz(u32 osc);
void sb_clk_output_48Mhz(void);
void sb_disable_4dw_burst(void);
void sb_enable(struct device *dev);
void southbridge_final(void *chip_info);

18
src/soc/amd/picasso/southbridge.c
View File

@ -190,26 +190,12 @@ static void sb_enable_legacy_io(void)
pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
}
void sb_clk_output_48Mhz(u32 osc)
void sb_clk_output_48Mhz(void)
{
u32 ctrl;
/*
* Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
* or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz.
*/
ctrl = misc_read32(MISC_CLK_CNTL1);
switch (osc) {
case 1:
ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
break;
case 2:
ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
break;
default:
return; /* do nothing if invalid */
}
ctrl |= BP_X48M0_OUTPUT_EN;
misc_write32(MISC_CLK_CNTL1, ctrl);
}