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{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro 

Use BIOS_CNTL defined macro instead of magic number.

Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Elyes HAOUAS 2018-12-01 12:19:52 +01:00 committed by Patrick Georgi
parent 9005071c5f
commit 0c22d2fe46
8 changed files with 6 additions and 108 deletions
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3
src/soc/intel/fsp_baytrail/southcluster.c
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@ -42,9 +42,6 @@
#include "chip.h" #include "chip.h"
#include <arch/acpi.h> #include <arch/acpi.h>
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct soc_intel_fsp_baytrail_config config_t; typedef struct soc_intel_fsp_baytrail_config config_t;
static inline void static inline void

4
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -436,9 +436,9 @@ static void pch_disable_smm_only_flashing(struct device *dev)
u8 reg8; u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(1 << 5); reg8 &= ~(1 << 5);
pci_write_config8(dev, 0xdc, reg8); pci_write_config8(dev, BIOS_CNTL, reg8);
} }
static void pch_fixups(struct device *dev) static void pch_fixups(struct device *dev)

3
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -38,9 +38,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_fsp_rangeley_config config_t; typedef struct southbridge_intel_fsp_rangeley_config config_t;
static void soc_enable_apic(struct device *dev) static void soc_enable_apic(struct device *dev)

32
src/southbridge/intel/i82801gx/lpc.c
View File

@ -40,7 +40,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_i82801gx_config config_t; typedef struct southbridge_intel_i82801gx_config config_t;
@ -333,10 +332,6 @@ static void enable_clock_gating(void)
#if CONFIG(HAVE_SMI_HANDLER) #if CONFIG(HAVE_SMI_HANDLER)
static void i82801gx_lock_smm(struct device *dev) static void i82801gx_lock_smm(struct device *dev)
{ {
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
#endif
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT #if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@ -351,33 +346,6 @@ static void i82801gx_lock_smm(struct device *dev)
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); outb(APM_CNT_ACPI_ENABLE, APM_CNT);
} }
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
#endif
} }
#endif #endif

32
src/southbridge/intel/i82801ix/lpc.c
View File

@ -39,7 +39,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_i82801ix_config config_t; typedef struct southbridge_intel_i82801ix_config config_t;
@ -370,10 +369,6 @@ static void enable_clock_gating(void)
#if CONFIG(HAVE_SMI_HANDLER) #if CONFIG(HAVE_SMI_HANDLER)
static void i82801ix_lock_smm(struct device *dev) static void i82801ix_lock_smm(struct device *dev)
{ {
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
#endif
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT #if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@ -393,33 +388,6 @@ static void i82801ix_lock_smm(struct device *dev)
*/ */
if (!CONFIG(PARALLEL_MP)) if (!CONFIG(PARALLEL_MP))
smm_lock(); smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
#endif
} }
#endif #endif

32
src/southbridge/intel/i82801jx/lpc.c
View File

@ -40,7 +40,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_i82801jx_config config_t; typedef struct southbridge_intel_i82801jx_config config_t;
@ -375,10 +374,6 @@ static void enable_clock_gating(void)
#if CONFIG(HAVE_SMI_HANDLER) #if CONFIG(HAVE_SMI_HANDLER)
static void i82801jx_lock_smm(struct device *dev) static void i82801jx_lock_smm(struct device *dev)
{ {
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
#endif
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT #if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@ -393,33 +388,6 @@ static void i82801jx_lock_smm(struct device *dev)
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); outb(APM_CNT_ACPI_ENABLE, APM_CNT);
} }
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
#endif
} }
#endif #endif

4
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -451,9 +451,9 @@ static void pch_disable_smm_only_flashing(struct device *dev)
u8 reg8; u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(1 << 5); reg8 &= ~(1 << 5);
pci_write_config8(dev, 0xdc, reg8); pci_write_config8(dev, BIOS_CNTL, reg8);
} }
static void pch_fixups(struct device *dev) static void pch_fixups(struct device *dev)

4
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -510,9 +510,9 @@ static void pch_disable_smm_only_flashing(struct device *dev)
u8 reg8; u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(1 << 5); reg8 &= ~(1 << 5);
pci_write_config8(dev, 0xdc, reg8); pci_write_config8(dev, BIOS_CNTL, reg8);
} }
static void pch_fixups(struct device *dev) static void pch_fixups(struct device *dev)