soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits

The definitions of bit 9 and 10 somehow got swapped between Picasso and
Renoir/Cezanne, so put those in the Cezanne-specific header file. The
reference code writes the same values to the raw bits in both, so we
probably would still get away with putting this into the common header,
but it's better to keep the defines consistent with the documentation in
all cases.

Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03
and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/include/soc/lpc.h

@@ -3,6 +3,12 @@
 #ifndef AMD_CEZANNE_LPC_H
 #define AMD_CEZANNE_LPC_H
 
+/* LPC_MISC_CONTROL_BITS at D14F3x078 */
+/* The definitions of bits 9 and 10 are swapped on Picasso and older compared to Renoir/Cezanne
+   and newer, so we need to keep those in a SoC-specific header file. */
+#define   LPC_LDRQ0_PU_EN		BIT(10)
+#define   LPC_LDRQ0_PD_EN		BIT(9)
+
 #define SPIROM_BASE_ADDRESS_REGISTER	0xa0
 #define   SPI_BASE_ALIGNMENT		BIT(8)
 #define   SPI_BASE_RESERVED		(BIT(5) | BIT(6) | BIT(7))

src/soc/amd/common/block/include/amdblocks/lpc.h

@@ -105,6 +105,8 @@
 #define   LPC_ALT_WIDEIO0_ENABLE	BIT(0)
 
 #define LPC_MISC_CONTROL_BITS		0x78
+#define   LPC_LDRQ1_EN			BIT(3)
+#define   LPC_LDRQ0_EN			BIT(2)
 #define   LPC_NOHOG			BIT(0)
 
 #define LPC_TRUSTED_PLATFORM_MODULE	0x7c