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soc/intel/apollolake: Add cache for BIOS ROM 

Enable caching of BIOS region with variable MTRR. This is most
useful if enabled early such as in bootblock.

Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Andrey Petrov 2016-04-23 12:31:01 -07:00 committed by Aaron Durbin
parent e976bd4469
commit 0c85b7f4d7
2 changed files with 22 additions and 0 deletions
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1
src/cpu/x86/mtrr/Makefile.inc
View File

@ -1,2 +1,3 @@
ramstage-y += mtrr.c
romstage-y += earlymtrr.c
bootblock-y += earlymtrr.c

21
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -16,7 +16,9 @@
*/
#include <arch/cpu.h>
#include <bootblock_common.h>
#include <cpu/x86/mtrr.h>
#include <device/pci.h>
#include <lib.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
@ -76,6 +78,24 @@ void asmlinkage bootblock_c_entry(void)
main();
}
static void cache_bios_region(void)
{
int mtrr;
uint32_t rom_size, alignment;
mtrr = get_free_var_mtrr();
if (mtrr==-1)
return;
/* Only the IFD BIOS region is memory mapped (at top of 4G) */
rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START;
/* Round to power of two */
alignment = 1 << (log2_ceil(rom_size));
rom_size = ALIGN_UP(rom_size, alignment);
set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
}
void bootblock_soc_early_init(void)
{
/* Prepare UART for serial console. */
@ -88,4 +108,5 @@ void bootblock_soc_early_init(void)
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC))
early_lpc_enable();
cache_bios_region();
}