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siemens/mc_apl3: Disable CLKREQ of PCIe root ports 

All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".

Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Mario Scheithauer 2018-11-06 10:35:57 +01:00 committed by Patrick Georgi
parent a29d4d2908
commit 0d0ebb6be9
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
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@ -7,10 +7,10 @@ chip soc/intel/apollolake
register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"