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src: Move POST_BOOTBLOCK_CAR to common postcodes and use it 

This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.

Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21.  This will
change the value on some platforms.

Any conflicts should get sorted out later in the conversion process.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Martin Roth 2022-12-31 18:27:22 -07:00 committed by Elyes Haouas
parent a891f71ad5
commit 0d34a50a36
5 changed files with 8 additions and 9 deletions
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6
src/commonlib/include/commonlib/console/post_codes.h
View File

@ -71,6 +71,12 @@
*/ */
#define POST_ENTRY_C_START 0x13 #define POST_ENTRY_C_START 0x13
/**
* \brief Entry into bootblock cache-as-RAM code
*
*/
#define POST_BOOTBLOCK_CAR 0x21
/** /**
* \brief Entry into pci_scan_bus * \brief Entry into pci_scan_bus
* *

3
src/cpu/qemu-x86/cache_as_ram_bootblock.S
View File

@ -15,7 +15,7 @@
bootblock_pre_c_entry: bootblock_pre_c_entry:
cache_as_ram: cache_as_ram:
post_code(0x20) post_code(POST_BOOTBLOCK_CAR)
/* /*
* Nothing to do here on qemu, RAM works just fine without any * Nothing to do here on qemu, RAM works just fine without any
* initialization. * initialization.
@ -103,7 +103,6 @@ pages_done:
#endif #endif
before_c_entry: before_c_entry:
post_code(0x29)
call bootblock_c_entry_bist call bootblock_c_entry_bist
/* Never returns */ /* Never returns */
.Lhlt: .Lhlt:

4
src/drivers/intel/fsp1_1/cache_as_ram.S
View File

@ -34,7 +34,7 @@ bootblock_pre_c_entry:
movd %eax, %mm1 movd %eax, %mm1
cache_as_ram: cache_as_ram:
post_code(0x20) post_code(POST_BOOTBLOCK_CAR)
/* Cache the rom and update the microcode */ /* Cache the rom and update the microcode */
cache_rom: cache_rom:
@ -181,8 +181,6 @@ CAR_init_done:
pushl %eax /* tsc[31:0] */ pushl %eax /* tsc[31:0] */
before_romstage: before_romstage:
post_code(0x2a)
/* Call bootblock_c_entry(uint64_t base_timestamp) */ /* Call bootblock_c_entry(uint64_t base_timestamp) */
call bootblock_c_entry call bootblock_c_entry

1
src/include/cpu/intel/post_codes.h
View File

@ -3,7 +3,6 @@
#ifndef CPU_INTEL_CAR_POST_CODES_H #ifndef CPU_INTEL_CAR_POST_CODES_H
#define CPU_INTEL_CAR_POST_CODES_H #define CPU_INTEL_CAR_POST_CODES_H
#define POST_BOOTBLOCK_CAR 0x20
#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 #define POST_SOC_SET_DEF_MTRR_TYPE 0x21
#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate #define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate
#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 #define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22

3
src/soc/intel/common/block/include/intelblocks/post_codes.h
View File

@ -16,9 +16,6 @@
#define POST_SOC_CAR_INIT_DONE 0x29 #define POST_SOC_CAR_INIT_DONE 0x29
#define POST_SOC_BEFORE_CARSTAGE 0x2a #define POST_SOC_BEFORE_CARSTAGE 0x2a
/* common/block/cpu/car/cache_as_ram_fsp.S */
#define POST_BOOTBLOCK_CAR 0x21
/* common/block/cse/cse.c */ /* common/block/cse/cse.c */
#define POST_CODE_ZERO 0x00 #define POST_CODE_ZERO 0x00
#endif #endif