GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake: add support for external source clock 

Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.

BUG=b:233252409
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Cliff Huang 2022-04-28 18:20:27 -07:00 committed by Felix Held
parent 61a442ec01
commit 0d590b7d91
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/alderlake/Kconfig
View File

@ -232,11 +232,17 @@ config MAX_ROOT_PORTS
default MAX_PCH_ROOT_PORTS default MAX_PCH_ROOT_PORTS
config MAX_PCIE_CLOCK_SRC config MAX_PCIE_CLOCK_SRC
prompt "Number of Source Clock supported from SOC"
int int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 7 if SOC_INTEL_ALDERLAKE_PCH_P
default 18 if SOC_INTEL_ALDERLAKE_PCH_S default 18 if SOC_INTEL_ALDERLAKE_PCH_S
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
help
With external clock buffer, Alderlake-P can support up to three additional source clocks.
This is done by setting the corresponding GPIO pin(s) to native function to use as
SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock.
If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on.
config MAX_PCIE_CLOCK_REQ config MAX_PCIE_CLOCK_REQ
int int