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soc/intel/alderlake: Add support for PCIe slot & device detect timeout 

1. add timeout for root port detection and pass to FSP.
2. add 'slot implemented' flag and pass to FSP.
3. PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
4. PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Cliff Huang 2022-04-28 18:06:54 -07:00 committed by Felix Held
parent 76ef18d8ff
commit 61a442ec01
2 changed files with 8 additions and 0 deletions
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4
src/soc/intel/alderlake/fsp_params.c
View File

@ -673,6 +673,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
if (rp_cfg->pcie_rp_aspm)
s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
/* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
s_cfg->PcieRpSlotImplemented[i] = 0;
s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
}
}

4
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@ -27,6 +27,8 @@ enum pcie_rp_flags {
PCIE_RP_CLK_REQ_DETECT = (1 << 4),
/* Clock request signal is not used by the root port. */
PCIE_RP_CLK_REQ_UNUSED = (1 << 5),
/* indicates that this root port is built-in. */
PCIE_RP_BUILT_IN = (1 << 6),
};
enum pcie_clk_src_flags {
@ -63,6 +65,8 @@ struct pcie_rp_config {
enum L1_substates_control PcieRpL1Substates;
/* PCIe RP ASPM */
enum ASPM_control pcie_rp_aspm;
/* timeout for device detect */
uint32_t pcie_rp_detect_timeout_ms;
};
/*