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glados: Fix incorrect comment format in devicetree.cb 

The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #.  Due to a last minute formatting
change in my commit to enable USB ports this broke the glados
build.

BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11553
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-08-31 09:49:08 -07:00 committed by Patrick Georgi
parent 2b9595a872
commit 0d65df93f0
1 changed files with 10 additions and 10 deletions
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20
src/mainboard/google/glados/devicetree.cb
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@ -20,17 +20,17 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoPci, \ [PchSerialIoIndexUart2] = PchSerialIoPci, \
}" }"
register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */ register "PortUsb20Enable[0]" = "1" # Type-C Port 1
register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */ register "PortUsb20Enable[1]" = "1" # Type-C Port 2
register "PortUsb20Enable[2]" = "1" /* Bluetooth */ register "PortUsb20Enable[2]" = "1" # Bluetooth
register "PortUsb20Enable[4]" = "1" /* Type-A Port 1 */ register "PortUsb20Enable[4]" = "1" # Type-A Port 1
register "PortUsb20Enable[6]" = "1" /* Camera */ register "PortUsb20Enable[6]" = "1" # Camera
register "PortUsb20Enable[8]" = "1" /* Type-A Port 2 */ register "PortUsb20Enable[8]" = "1" # Type-A Port 2
register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */ register "PortUsb30Enable[0]" = "1" # Type-C Port 1
register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */ register "PortUsb30Enable[1]" = "1" # Type-C Port 2
register "PortUsb30Enable[2]" = "1" /* Type-A Port 1 */ register "PortUsb30Enable[2]" = "1" # Type-A Port 1
register "PortUsb30Enable[3]" = "1" /* Type-A Port 2 */ register "PortUsb30Enable[3]" = "1" # Type-A Port 2
# Enable Root port 1 and 5. # Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1" register "PcieRpEnable[0]" = "1"