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soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree 

This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.

BUG=None
BRANCH=None
TEST=Build and boot tglrvp.

Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Meera Ravindranath 2020-04-29 12:19:33 +05:30 committed by Patrick Georgi
parent 4c7bc8db74
commit 0d6cc22017
2 changed files with 8 additions and 0 deletions
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3
src/soc/intel/tigerlake/chip.h
View File

@ -107,6 +107,9 @@ struct soc_intel_tigerlake_config {
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,

5
src/soc/intel/tigerlake/fsp_params.c
View File

@ -151,6 +151,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i];
}
/* Enable ClkReqDetect for enabled port */
memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
sizeof(config->PcieRpClkReqDetect));
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) {