Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1422 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
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@ -25,6 +25,7 @@ config CPU_AMD_AGESA
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default y if CPU_AMD_AGESA_FAMILY15
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default n
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select TSC_SYNC_LFENCE
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if CPU_AMD_AGESA
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@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX
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select SSE
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select SSE2
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select MMCONF_SUPPORT_DEFAULT
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select TSC_SYNC_LFENCE
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if CPU_AMD_MODEL_10XXX
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config CPU_ADDR_BITS
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@ -3,6 +3,7 @@ config CPU_AMD_MODEL_FXX
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select MMX
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select SSE
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select SSE2
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select TSC_SYNC_LFENCE
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if CPU_AMD_MODEL_FXX
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config UDELAY_IO
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@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_1067X
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bool
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select SMP
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select SSE2
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select TSC_SYNC_MFENCE
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@ -4,9 +4,9 @@ config CPU_INTEL_MODEL_106CX
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select SSE2
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select UDELAY_LAPIC
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select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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config CPU_ADDR_BITS
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int
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default 32
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@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
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select SMM_TSEG
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select MICROCODE_IN_CBFS
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#select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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config BOOTBLOCK_CPU_INIT
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string
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@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6EX
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select SSE2
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select UDELAY_LAPIC
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select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6FX
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select SSE2
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select UDELAY_LAPIC
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select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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@ -23,6 +23,22 @@ config TSC_CALIBRATE_WITH_IO
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bool
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default n
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config XIP_ROM_SIZE
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hex
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default ROM_SIZE if ROMCC
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@ -1,6 +1,14 @@
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#ifndef CPU_X86_TSC_H
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#define CPU_X86_TSC_H
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#if CONFIG_TSC_SYNC_MFENCE
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#define TSC_SYNC "mfence\n"
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#elif CONFIG_TSC_SYNC_LFENCE
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#define TSC_SYNC "lfence\n"
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#else
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#define TSC_SYNC
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#endif
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struct tsc_struct {
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unsigned lo;
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unsigned hi;
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@ -10,10 +18,11 @@ typedef struct tsc_struct tsc_t;
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static inline tsc_t rdtsc(void)
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{
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tsc_t res;
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__asm__ __volatile__ (
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asm volatile (
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TSC_SYNC
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"rdtsc"
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: "=a" (res.lo), "=d"(res.hi) /* outputs */
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);
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);
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return res;
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}
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@ -22,7 +31,11 @@ static inline tsc_t rdtsc(void)
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static inline unsigned long long rdtscll(void)
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{
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unsigned long long val;
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asm volatile ("rdtsc" : "=A" (val));
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asm volatile (
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TSC_SYNC
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"rdtsc"
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: "=A" (val)
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);
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return val;
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}
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#endif
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