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soc/intel/common: Add function to lpc_lib to return PIRQ routing 

In order to fill out static entries for a _PRT table for
soc/intel/common, the PIRQ<->IRQ mapping is required. This patch adds
a function lpc_get_pch_pirq_routing() which returns this mapping.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tim Wawrzynczak 2021-02-04 17:04:24 -07:00 committed by Patrick Georgi
parent fae418777d
commit 0dc82cc80b
4 changed files with 24 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/common/block/include/intelblocks/itss.h
View File

@ -3,9 +3,6 @@
#ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H
#define SOC_INTEL_COMMON_BLOCK_ITSS_H #define SOC_INTEL_COMMON_BLOCK_ITSS_H
/* Max PXRC registers in ITSS*/
#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
/* PIRQA Routing Control Register*/ /* PIRQA Routing Control Register*/
#define PCR_ITSS_PIRQA_ROUT 0x3100 #define PCR_ITSS_PIRQA_ROUT 0x3100
/* PIRQB Routing Control Register*/ /* PIRQB Routing Control Register*/
@ -29,6 +26,7 @@
#if !defined(__ACPI__) #if !defined(__ACPI__)
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <stdint.h> #include <stdint.h>
/* Set the interrupt polarity for provided IRQ to the APIC. */ /* Set the interrupt polarity for provided IRQ to the APIC. */
@ -38,7 +36,7 @@ void itss_set_irq_polarity(int irq, int active_low);
void itss_snapshot_irq_polarities(int start, int end); void itss_snapshot_irq_polarities(int start, int end);
void itss_restore_irq_polarities(int start, int end); void itss_restore_irq_polarities(int start, int end);
void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]); void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT]);
void itss_clock_gate_8254(void); void itss_clock_gate_8254(void);
#endif /* !defined(__ACPI__) */ #endif /* !defined(__ACPI__) */

2
src/soc/intel/common/block/include/intelblocks/lpc_lib.h
View File

@ -105,5 +105,5 @@ void pch_misc_init(void);
unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long southbridge_write_acpi_tables(const struct device *device,
unsigned long current, unsigned long current,
struct acpi_rsdp *rsdp); struct acpi_rsdp *rsdp);
const uint8_t *lpc_get_pic_pirq_routing(size_t *num);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */

5
src/soc/intel/common/block/itss/itss.c
View File

@ -7,10 +7,11 @@
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <soc/itss.h> #include <soc/itss.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
void itss_irq_init(uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]) void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT])
{ {
uint32_t regs[MAX_PXRC_CONFIG/sizeof(uint32_t)] = {0}; uint32_t regs[PIRQ_COUNT/sizeof(uint32_t)] = {0};
uint8_t index, byte; uint8_t index, byte;
/* Fill in all the PIRx routes into one array. */ /* Fill in all the PIRx routes into one array. */

29
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -15,6 +15,7 @@
#include <soc/irq.h> #include <soc/irq.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
{ {
@ -297,6 +298,23 @@ void pch_enable_ioapic(void)
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
} }
static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
[PIRQ_A] = PCH_IRQ11,
[PIRQ_B] = PCH_IRQ10,
[PIRQ_C] = PCH_IRQ11,
[PIRQ_D] = PCH_IRQ11,
[PIRQ_E] = PCH_IRQ11,
[PIRQ_F] = PCH_IRQ11,
[PIRQ_G] = PCH_IRQ11,
[PIRQ_H] = PCH_IRQ11,
};
const uint8_t *lpc_get_pic_pirq_routing(size_t *num)
{
*num = ARRAY_SIZE(pch_interrupt_routing);
return pch_interrupt_routing;
}
/* /*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved * 0x00 - 0000 = Reserved
@ -321,17 +339,6 @@ void pch_enable_ioapic(void)
void pch_pirq_init(void) void pch_pirq_init(void)
{ {
const struct device *irq_dev; const struct device *irq_dev;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing); itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {