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soc/intel/apollolake: Handle CAR sizes other than 1 MiB 

Since whole L2 (1MiB) is not used, it is possible to shrink CAR size
to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to
set it up. This is a part of CQOS enabling.

BUG=chrome-os-partner:51959

Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15453
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-06-27 15:21:26 -07:00 committed by Martin Roth
parent 7c8d74c103
commit 0dde2917a5
2 changed files with 28 additions and 1 deletions
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2
src/soc/intel/apollolake/Kconfig
View File

@ -97,7 +97,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM" hex "Length in bytes of cache-as-RAM"
default 0x100000 default 0xc0000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
and/or romstage. and/or romstage.

27
src/soc/intel/apollolake/bootblock/cache_as_ram.S
View File

@ -17,6 +17,7 @@
*/ */
#include <device/pci_def.h> #include <device/pci_def.h>
#include <commonlib/helpers.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/cr.h> #include <cpu/x86/cr.h>
@ -70,6 +71,7 @@ clear_var_mtrr:
post_code(0x24) post_code(0x24)
#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
/* Configure CAR region as write-back (WB) */ /* Configure CAR region as write-back (WB) */
mov $MTRR_PHYS_BASE(0), %ecx mov $MTRR_PHYS_BASE(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax mov $CONFIG_DCACHE_RAM_BASE, %eax
@ -82,6 +84,31 @@ clear_var_mtrr:
mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */
or $MTRR_PHYS_MASK_VALID, %eax or $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
mov $MTRR_PHYS_BASE(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
mov $MTRR_PHYS_MASK(0), %ecx
mov $~(512 * KiB - 1), %eax /* size mask */
or $MTRR_PHYS_MASK_VALID, %eax
wrmsr
mov $MTRR_PHYS_BASE(1), %ecx
mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
mov $MTRR_PHYS_MASK(1), %ecx
mov $~(256 * KiB - 1), %eax /* size mask */
or $MTRR_PHYS_MASK_VALID, %eax
wrmsr
#else
#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
#endif
post_code(0x25) post_code(0x25)