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soc/intel/{cnl, icl}: Cache the TSEG region 

This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.

BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot

Without this CL:
Total Time: 929ms

With this CL: (TSEG marked as WB)
Total Time: 910ms

For test marked TSEG as WP/WC:
Total Time: ~920ms

Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-09-10 16:00:08 +05:30
parent 3eff037f8c
commit 0e3c245c6c
2 changed files with 6 additions and 0 deletions
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3
src/soc/intel/cannonlake/memmap.c
View File

@ -280,4 +280,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB; top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
} }

3
src/soc/intel/icelake/memmap.c
View File

@ -278,4 +278,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB; top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
} }