soc/intel/apollolake: Work around FSP-M CAR layout
As of now FSP-M can not be relocated and it can not be instructed to use a specific resource for temporary memory. As result coreboot is forced to use CAR layout dictated by default FSP-M configuration. Change CAR size to 1MiB, link romstage at such CAR address so it doesn't overlap with FSP-M's default heap/stack. Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -73,7 +73,7 @@ config DCACHE_RAM_BASE
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config DCACHE_RAM_SIZE
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hex "Length in bytes of cache-as-RAM"
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default 0x80000
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default 0x100000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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@ -116,7 +116,7 @@ config X86_TOP4G_BOOTMEDIA_MAP
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config ROMSTAGE_ADDR
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hex
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default 0xfef2e000
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default 0xfef3e000
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help
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The base address (in CAR) where romstage should be linked
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