0e46307574
As of now FSP-M can not be relocated and it can not be instructed to use a specific resource for temporary memory. As result coreboot is forced to use CAR layout dictated by default FSP-M configuration. Change CAR size to 1MiB, link romstage at such CAR address so it doesn't overlap with FSP-M's default heap/stack. Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
127 lines
2.7 KiB
Text
127 lines
2.7 KiB
Text
config SOC_INTEL_APOLLOLAKE
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bool
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help
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Intel Apollolake support
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if SOC_INTEL_APOLLOLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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# CPU specific options
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select IOAPIC
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select SMP
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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# Misc options
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select C_ENVIRONMENT_BOOTBLOCK
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select COLLECT_TIMESTAMPS
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select COMMON_FADT
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select HAVE_INTEL_FIRMWARE
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select NO_FIXED_XIP_ROM_SIZE
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select NO_STAGE_CACHE
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select NO_XIP_EARLY_STAGES
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select POSTCAR_STAGE
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select REG_SCRIPT
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select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
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select SOC_INTEL_COMMON
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select SPI_FLASH
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select HAVE_MONOTONIC_TIMER
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select PLATFORM_USES_FSP2_0
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select HAVE_HARD_RESET
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_GFX_OPREGION
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select ADD_VBT_DATA_FILE
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config TPM_ON_FAST_SPI
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bool
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default n
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select LPC_TPM
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help
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TPM part is conntected on Fast SPI interface, but the LPC MMIO
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TPM transactions are decoded and serialized over the SPI interface.
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config SOC_INTEL_COMMON_RESET
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bool
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default y
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config MMCONF_BASE_ADDRESS
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hex "PCI MMIO Base Address"
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default 0xe0000000
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config IOSF_BASE_ADDRESS
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hex "MMIO Base Address of sideband bus"
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default 0xd0000000
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config DCACHE_RAM_BASE
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hex "Base address of cache-as-RAM"
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex "Length in bytes of cache-as-RAM"
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default 0x100000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config CPU_ADDR_BITS
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int
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default 36
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL
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hex "MMIO base address for UART"
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default 0xde000000
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config SOC_UART_DEBUG
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bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
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default n
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select CONSOLE_SERIAL
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x8000
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# This SoC does not map SPI flash like many previous SoC. Therefore we provide
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# a custom media driver that facilitates mapping
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config X86_TOP4G_BOOTMEDIA_MAP
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bool
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default n
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config ROMSTAGE_ADDR
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hex
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default 0xfef3e000
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help
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The base address (in CAR) where romstage should be linked
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config CACHE_MRC_SETTINGS
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bool
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default y
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endif
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