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soc/intel/apollolake: Work around FSP-M CAR layout 

As of now FSP-M can not be relocated and it can not be instructed
to use a specific resource for temporary memory. As result coreboot
is forced to use CAR layout dictated by default FSP-M configuration.

Change CAR size to 1MiB, link romstage at such CAR address so it
doesn't overlap with FSP-M's default heap/stack.

Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14804
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Andrey Petrov 2016-04-23 14:28:21 -07:00 committed by Aaron Durbin
parent 5ede3d8cce
commit 0e46307574
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/apollolake/Kconfig
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@ -73,7 +73,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM" hex "Length in bytes of cache-as-RAM"
default 0x80000 default 0x100000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
and/or romstage. and/or romstage.
@ -116,7 +116,7 @@ config X86_TOP4G_BOOTMEDIA_MAP
config ROMSTAGE_ADDR config ROMSTAGE_ADDR
hex hex
default 0xfef2e000 default 0xfef3e000
help help
The base address (in CAR) where romstage should be linked The base address (in CAR) where romstage should be linked