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soc/amd: Move acpi_fill_mcfg into common/blocks/acpi

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This is common between stoney, picasso, and cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-02-11 10:10:57 -07:00 committed by Martin Roth
parent 0f3bc81210
commit 0e560e7015
3 changed files with 12 additions and 24 deletions
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12
src/soc/amd/common/block/acpi/tables.c
View file

@ -11,3 +11,15 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
{
return acpi_write_hpet(device, current, rsdp);
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
CONFIG_MMCONF_BASE_ADDRESS,
0,
0,
CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

12
src/soc/amd/picasso/acpi.c
View file

@ -29,18 +29,6 @@
#include <version.h>
#include "chip.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
CONFIG_MMCONF_BASE_ADDRESS,
0,
0,
CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
const struct soc_amd_picasso_config *cfg = config_of_soc();

12
src/soc/amd/stoneyridge/northbridge.c
View file

@ -162,18 +162,6 @@ static void northbridge_init(struct device *dev)
setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
CONFIG_MMCONF_BASE_ADDRESS,
0,
0,
CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
{
void *addr, *current;