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intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS 

Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called
to enumerate SGX resources.

Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Pratik Prajapati 2017-10-11 11:48:04 -07:00 committed by Aaron Durbin
parent 90ebf96df5
commit 0e5eb46bb7
3 changed files with 51 additions and 0 deletions
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9
src/soc/intel/common/block/include/intelblocks/msr.h
View File

@ -130,4 +130,13 @@
#define PRMRR_SUPPORTED (1<<12)
#define SGX_SUPPORTED (1<<2)
/* Intel SDM: Table 36-6.
* CPUID Leaf 12H, Sub-Leaf Index 2 or Higher for enumeration of
* SGX Resources. Same Table mentions about return values of the CPUID */
#define SGX_RESOURCE_ENUM_CPUID_LEAF (0x12)
#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF (0x2)
#define SGX_RESOURCE_ENUM_BIT (0x1)
#define SGX_RESOURCE_MASK_LO (0xfffff000UL)
#define SGX_RESOURCE_MASK_HI (0xfffffUL)
#endif /* SOC_INTEL_COMMON_MSR_H */

5
src/soc/intel/common/block/include/intelblocks/sgx.h
View File

@ -16,6 +16,8 @@
#ifndef SOC_INTEL_COMMON_BLOCK_SGX_H
#define SOC_INTEL_COMMON_BLOCK_SGX_H
#include <soc/nvs.h>
struct sgx_param {
uint8_t enable;
};
@ -42,4 +44,7 @@ void sgx_configure(void);
* returns 0, if able to get SGX params; otherwise returns -1 */
int soc_fill_sgx_param(struct sgx_param *sgx_param);
/* Fill GNVS data with SGX status, EPC base and length */
void sgx_fill_gnvs(global_nvs_t *gnvs);
#endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */

37
src/soc/intel/common/block/sgx/sgx.c
View File

@ -29,6 +29,14 @@
static bool sgx_param_valid;
static struct sgx_param g_sgx_param;
static inline uint64_t sgx_resource(uint32_t low, uint32_t high)
{
uint64_t val;
val = (uint64_t)(high & SGX_RESOURCE_MASK_HI) << 32;
val |= low & SGX_RESOURCE_MASK_LO;
return val;
}
static const struct sgx_param *get_sgx_param(void)
{
if (sgx_param_valid)
@ -222,3 +230,32 @@ void sgx_configure(void)
if (is_prmrr_approved())
activate_sgx();
}
void sgx_fill_gnvs(global_nvs_t *gnvs)
{
struct cpuid_result cpuid_regs;
if (!soc_sgx_enabled() || !is_sgx_supported()) {
printk(BIOS_DEBUG,
"SGX: not enabled or not supported. skip gnvs fill\n");
return;
}
/* Get EPC base and size.
* Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or
* Higher for enumeration of SGX Resources. Same Table mentions
* about return values of the CPUID */
cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,
SGX_RESOURCE_ENUM_CPUID_SUBLEAF);
if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {
/* EPC section enumerated */
gnvs->ecps = 1;
gnvs->emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx);
gnvs->elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx);
}
printk(BIOS_DEBUG,
"SGX: gnvs ECP status = %d base = 0x%llx len = 0x%llx\n",
gnvs->ecps, gnvs->emna, gnvs->elng);
}