soc/intel/skylake: Add GNVS variables and include SGX ASL

- Add GNVS variables for SGX
- Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Pratik Prajapati 2017-10-11 16:11:43 -07:00 committed by Aaron Durbin
parent 03a2353df6
commit 90ebf96df5
3 changed files with 11 additions and 0 deletions

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@ -67,6 +67,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
UIOR, 8, // 0x42 - UART debug controller init on S3 resume
EPCS, 8, // 0x43 - SGX Enabled status
EMNA, 64, // 0x44 - 0x4B EPC base address
ELNG, 64, // 0x4C - 0x53 EPC Length
/* ChromeOS specific */
Offset (0x100),

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@ -72,3 +72,8 @@ Method (_OSC, 4)
Return (Arg3)
}
}
/* SGX */
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
#include <soc/intel/common/acpi/sgx.asl>
#endif

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@ -58,6 +58,9 @@ typedef struct {
u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */
u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */
u8 uior; /* 0x42 - UART debug controller init on S3 resume */
u8 ecps; /* 0x43 - SGX Enabled status */
u64 emna; /* 0x44 - 0x4B EPC base address */
u64 elng; /* 0x4C - 0x53 EPC Length */
u8 unused[189];
/* ChromeOS specific (0x100 - 0xfff) */