soc/intel/skylake: Add GNVS variables and include SGX ASL
- Add GNVS variables for SGX - Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set - With this patch SGX ACPI device would get created and kernel SGX driver would let loaded Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -67,6 +67,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
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U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
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UIOR, 8, // 0x42 - UART debug controller init on S3 resume
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EPCS, 8, // 0x43 - SGX Enabled status
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EMNA, 64, // 0x44 - 0x4B EPC base address
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ELNG, 64, // 0x4C - 0x53 EPC Length
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/* ChromeOS specific */
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Offset (0x100),
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@ -72,3 +72,8 @@ Method (_OSC, 4)
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Return (Arg3)
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}
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}
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/* SGX */
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#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
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#include <soc/intel/common/acpi/sgx.asl>
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#endif
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@ -58,6 +58,9 @@ typedef struct {
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u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */
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u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */
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u8 uior; /* 0x42 - UART debug controller init on S3 resume */
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u8 ecps; /* 0x43 - SGX Enabled status */
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u64 emna; /* 0x44 - 0x4B EPC base address */
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u64 elng; /* 0x4C - 0x53 EPC Length */
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u8 unused[189];
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/* ChromeOS specific (0x100 - 0xfff) */
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