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mb/google/brya/var/primus{4es}: add enable pin to rtd3-cold 

Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     test suspend stress 100 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2022-03-04 14:08:01 +08:00 committed by Tim Wawrzynczak
parent 42c460d3e5
commit 0e834a9455
2 changed files with 2 additions and 0 deletions
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1
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@ -144,6 +144,7 @@ chip soc/intel/alderlake
device ref pcie_rp3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "6"
device generic 0 alias emmc_rtd3 on end
end

1
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@ -138,6 +138,7 @@ chip soc/intel/alderlake
device ref pcie_rp3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "6"
device generic 0 alias emmc_rtd3 on end
end