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mb/google/brya/var/crota: update gpio configuration 

- enable CPU PCIe VGPIO for PEG60
- enable GPP_C3/ GPP_C4 native function
- set unused GPIO to NC

BUG=b:229584785
BRANCH=none
TEST=build and boot into kernel v5.10

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Scott Chao 2022-04-19 19:09:35 +08:00 committed by Felix Held
parent c480707986
commit 0ed3dfc92a
1 changed files with 37 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
src/mainboard/google/brya/variants/crota/gpio.c
View File

@ -7,6 +7,8 @@
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* A6 : ESPI_ALERT1# ==> NC */
PAD_NC(GPP_A6, NONE),
/* A19 : DDSP_HPD1 ==> NC */
PAD_NC(GPP_A19, NONE),
/* A20 : DDSP_HPD2 ==> NC */
@ -16,17 +18,22 @@ static const struct pad_config override_gpio_table[] = {
/* A22 : DDPC_CTRLDATA ==> NC */
PAD_NC(GPP_A22, NONE),
/* C3 : SML0CLK ==> SML0_SMBCLK */
PAD_CFG_GPO(GPP_C3, 0, DEEP),
/* C4 : SML0DATA ==> SML0_SMBDATA */
PAD_CFG_GPO(GPP_C4, 0, DEEP),
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE),
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE),
/* C3 : GPP_C3 ==> SML0_SMBCLK */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
/* C4 : GPP_C4 ==> SML0_SMBDATA */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* D13 : ISH_UART0_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
/* D14 : ISH_UART0_TXD ==> NC */
@ -51,6 +58,8 @@ static const struct pad_config override_gpio_table[] = {
/* E23 : DDPA_CTRLDATA ==> NC */
PAD_NC(GPP_E23, NONE),
/* F19 : SRCCLKREQ6# ==> NC */
PAD_NC(GPP_F19, NONE),
/* F20 : EXT_PWR_GATE# ==> NC */
PAD_NC(GPP_F20, NONE),
@ -139,6 +148,28 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, PLTRST),
/* CPU PCIe VGPIO for PEG60 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
};
static const struct pad_config romstage_gpio_table[] = {