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exynos5420: ddr3: Cleanup init to use constants for directcmd 

The old ddr3_mem_ctrl_init() for exynos5420 had hardcoded constants
for accessing directcmd registers.  Modify to use #defines where
possible.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/65616
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I01567fc6941608a570832de97259c55e84942d01
Reviewed-on: https://gerrit.chromium.org/gerrit/66789
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit d751e019f450172f060ce255ae53e972bc4a19ea)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
David Hendricks 2013-08-22 18:45:10 -07:00 committed by Isaac Christensen
parent 2f3daddd28
commit 0f0c720621
1 changed files with 21 additions and 16 deletions
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37
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
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@ -264,10 +264,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
nLockR |= nLockW_phy1; nLockR |= nLockW_phy1;
writel(nLockR, &phy1_ctrl->phy_con12); writel(nLockR, &phy1_ctrl->phy_con12);
writel(0x00030004, &drex0->directcmd); val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
writel(0x00130004, &drex0->directcmd); writel(val, &drex0->directcmd);
writel(0x00030004, &drex1->directcmd); writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
writel(0x00130004, &drex1->directcmd); writel(val, &drex1->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
@ -316,16 +317,19 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(0, &phy0_ctrl->phy_con14); writel(0, &phy0_ctrl->phy_con14);
writel(0, &phy1_ctrl->phy_con14); writel(0, &phy1_ctrl->phy_con14);
writel(0x00030000, &drex0->directcmd); val = (0x3 << DIRECT_CMD_BANK_SHIFT);
writel(0x00130000, &drex0->directcmd); writel(val, &drex0->directcmd);
writel(0x00030000, &drex1->directcmd); writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
writel(0x00130000, &drex1->directcmd); writel(val, &drex1->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
/* Set Read DQ Calibration */ /* Set Read DQ Calibration */
writel(0x00030004, &drex0->directcmd); val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
writel(0x00130004, &drex0->directcmd); writel(val, &drex0->directcmd);
writel(0x00030004, &drex1->directcmd); writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
writel(0x00130004, &drex1->directcmd); writel(val, &drex1->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
val = readl(&phy0_ctrl->phy_con1); val = readl(&phy0_ctrl->phy_con1);
val |= READ_LEVELLING_DDR3; val |= READ_LEVELLING_DDR3;
@ -371,10 +375,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
clrbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE); clrbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE);
writel(0x00030000, &drex0->directcmd); val = (0x3 << DIRECT_CMD_BANK_SHIFT);
writel(0x00130000, &drex0->directcmd); writel(val, &drex0->directcmd);
writel(0x00030000, &drex1->directcmd); writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
writel(0x00130000, &drex1->directcmd); writel(val, &drex1->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
update_reset_dll(drex0, DDR_MODE_DDR3); update_reset_dll(drex0, DDR_MODE_DDR3);
update_reset_dll(drex1, DDR_MODE_DDR3); update_reset_dll(drex1, DDR_MODE_DDR3);