arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -222,8 +222,9 @@ config VERSTAGE_ADDR
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# Use the post CAR infrastructure for tearing down cache-as-ram
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# from a program loaded in RAM and subsequently loading ramstage.
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config POSTCAR_STAGE
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def_bool n
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select NO_CAR_GLOBAL_MIGRATION
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def_bool y
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depends on ARCH_X86
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depends on !CAR_GLOBAL_MIGRATION
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config VERSTAGE_DEBUG_SPINLOOP
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bool
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@ -76,7 +76,7 @@
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* cbmem console. This is useful for clearing this area on a per-stage
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* basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
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_car_global_start = .;
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#if CONFIG(NO_CAR_GLOBAL_MIGRATION)
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#if !CONFIG(CAR_GLOBAL_MIGRATION)
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/* Allow global unitialized variables when CAR_GLOBALs are not used. */
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*(.bss)
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*(.bss.*)
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@ -84,7 +84,7 @@
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*(.sbss.*)
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#else
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/* .car.global_data objects only around when
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* !CONFIG_NO_CAR_GLOBAL_MIGRATION is employed. */
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* CONFIG_CAR_GLOBAL_MIGRATION is employed. */
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*(.car.global_data);
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#endif
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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@ -107,7 +107,7 @@
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.illegal_globals . : {
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
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#if !CONFIG(NO_CAR_GLOBAL_MIGRATION)
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#if CONFIG(CAR_GLOBAL_MIGRATION)
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*(.bss)
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*(.bss.*)
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*(.sbss)
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@ -20,7 +20,7 @@
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#include <commonlib/helpers.h>
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#include <stdlib.h>
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#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION)
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#if ENV_CACHE_AS_RAM && CONFIG(CAR_GLOBAL_MIGRATION)
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asm(".section .car.global_data,\"w\",@nobits");
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asm(".previous");
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#ifdef __clang__
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@ -83,8 +83,8 @@ static inline size_t car_object_offset(void *ptr)
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/*
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* We might end up here if:
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* 1. ENV_CACHE_AS_RAM is not set for the stage or
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* 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_NO_CAR_GLOBAL_MIGRATION
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* is also set. In this case, there is no need to migrate CAR global
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* 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_CAR_GLOBAL_MIGRATION
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* is not set. In this case, there is no need to migrate CAR global
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* variables. But, since we might still be running out of CAR, car_active needs
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* to return 1 if ENV_CACHE_AS_RAM is set.
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*/
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@ -101,6 +101,6 @@ static inline int car_active(void) { return 0; }
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#define car_get_var(var) (var)
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#define car_sync_var(var) (var)
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#define car_set_var(var, val) (var) = (val)
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#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */
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#endif /* ENV_CACHE_AS_RAM && CONFIG(CAR_GLOBAL_MIGRATION) */
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#endif /* ARCH_EARLY_VARIABLES_H */
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@ -10,12 +10,12 @@ config CACHE_AS_RAM
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bool
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default y
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config NO_CAR_GLOBAL_MIGRATION
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config CAR_GLOBAL_MIGRATION
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bool
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default n
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depends on CACHE_AS_RAM
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help
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This option is selected if there is no need to migrate CAR globals.
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This option is selected if there is need to migrate CAR globals.
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All stages which use CAR globals can directly access the variables
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from their linked addresses.
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@ -29,7 +29,6 @@ config CPU_AMD_AGESA
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select UDELAY_LAPIC
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select LAPIC_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select POSTCAR_STAGE
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select SMM_ASEG
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if CPU_AMD_AGESA
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@ -9,6 +9,7 @@ config CPU_AMD_MODEL_10XXX
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select UDELAY_LAPIC
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_MICROCODE_MULTIPLE_FILES
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select CAR_GLOBAL_MIGRATION
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select ACPI_HUGE_LOWMEM_BACKUP
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if CPU_AMD_MODEL_10XXX
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@ -28,7 +28,7 @@ config CPU_AMD_PI
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select UDELAY_LAPIC
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select LAPIC_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER
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select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
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select SMM_ASEG
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if CPU_AMD_PI
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@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
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select MMX
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CAR_GLOBAL_MIGRATION
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config DCACHE_RAM_BASE
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hex
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@ -1,5 +1,5 @@
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ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
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ifneq ($(CONFIG_NO_CAR_GLOBAL_MIGRATION),y)
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ifeq ($(CONFIG_CAR_GLOBAL_MIGRATION),y)
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romstage-$(CONFIG_CACHE_AS_RAM) += car.c
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endif
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endif
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@ -16,6 +16,7 @@
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config PLATFORM_USES_FSP1_0
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bool
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default n
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select CAR_GLOBAL_MIGRATION
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help
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Selected for Intel processors/platform combinations that use the
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Intel Firmware Support Package (FSP) 1.0 for initialization.
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@ -18,7 +18,6 @@ config PLATFORM_USES_FSP1_1
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bool
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select UEFI_2_4_BINDING
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select POSTCAR_STAGE
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help
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Does the code require the Intel Firmware Support Package?
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@ -41,7 +41,7 @@
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*/
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#define CAN_USE_GLOBALS \
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(!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \
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CONFIG(NO_CAR_GLOBAL_MIGRATION))
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!CONFIG(CAR_GLOBAL_MIGRATION))
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static inline struct imd *cbmem_get_imd(void)
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{
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@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS
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select BOARD_ROMSIZE_KB_256
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select POSTCAR_STAGE
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config MAINBOARD_DIR
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string
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
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select BOARD_ROMSIZE_KB_2048
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select POSTCAR_STAGE
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config MAINBOARD_DIR
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string
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@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_TPM2
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select PLATFORM_USES_FSP2_0
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select UDK_2015_BINDING
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select POSTCAR_STAGE
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config MAINBOARD_DIR
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@ -22,6 +22,5 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select POSTCAR_STAGE
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endif
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@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select INTEL_EDID
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select INTEL_GMA_ACPI
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select INTEL_GMA_SSC_ALTERNATE_REF
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select POSTCAR_STAGE
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select PARALLEL_MP
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config CBFS_SIZE
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@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL
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select CACHE_MRC_SETTINGS
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select INTEL_DDI
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select INTEL_GMA_ACPI
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select POSTCAR_STAGE
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select C_ENVIRONMENT_BOOTBLOCK
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select BOOTBLOCK_CONSOLE
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@ -18,7 +18,6 @@ config NORTHBRIDGE_INTEL_I440BX
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select UDELAY_IO
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select POSTCAR_STAGE
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config SDRAMPWR_4DIMM
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bool
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@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select INTEL_GMA_SSC_ALTERNATE_REF
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select INTEL_EDID
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select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select POSTCAR_STAGE
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select PARALLEL_MP
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config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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@ -20,7 +20,6 @@ config NORTHBRIDGE_INTEL_NEHALEM
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select INTEL_EDID
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select INTEL_GMA_ACPI
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select CACHE_MRC_SETTINGS
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select POSTCAR_STAGE
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select HAVE_DEBUG_RAM_SETUP
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if NORTHBRIDGE_INTEL_NEHALEM
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@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
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select INTEL_GMA_ACPI
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select POSTCAR_STAGE
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select PARALLEL_MP
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select C_ENVIRONMENT_BOOTBLOCK
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@ -20,7 +20,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
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select CPU_INTEL_MODEL_206AX
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select HAVE_DEBUG_RAM_SETUP
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select INTEL_GMA_ACPI
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select POSTCAR_STAGE
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if NORTHBRIDGE_INTEL_SANDYBRIDGE
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@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select VGA
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select INTEL_GMA_ACPI
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select CACHE_MRC_SETTINGS
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select POSTCAR_STAGE
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select PARALLEL_MP
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config CBFS_SIZE
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@ -56,7 +56,6 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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select POSTCAR_STAGE
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select SSE2
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select RTC
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@ -76,7 +76,6 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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select POSTCAR_STAGE
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select SSE2
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select RTC
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@ -57,7 +57,6 @@ config CPU_SPECIFIC_OPTIONS
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select PCIEX_LENGTH_256MB
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select POSTCAR_STAGE
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select PMC_INVALID_READ_AFTER_WRITE
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select PMC_GLOBAL_RESET_ENABLE_LOCK
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select REG_SCRIPT
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@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SPI_CONSOLE_SUPPORT
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select INTEL_GMA_ACPI
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select INTEL_GMA_SWSMISCI
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select POSTCAR_STAGE
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select CPU_INTEL_COMMON
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select CPU_HAS_L2_ENABLE_MSR
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@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SPI_CONSOLE_SUPPORT
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select CPU_INTEL_COMMON
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select INTEL_GMA_ACPI
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select POSTCAR_STAGE
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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select NO_FIXED_XIP_ROM_SIZE
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@ -76,7 +76,6 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PLATFORM_USES_FSP2_0
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select POSTCAR_STAGE
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select REG_SCRIPT
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select SMP
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select SOC_AHCI_PORT_IMPLEMENTED_INVERT
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@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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select PLATFORM_USES_FSP2_0
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select POSTCAR_STAGE
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select C_ENVIRONMENT_BOOTBLOCK
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select IOAPIC
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select HAVE_SMI_HANDLER
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@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
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select PARALLEL_MP_AP_WORK
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select MICROCODE_BLOB_UNDISCLOSED
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select PLATFORM_USES_FSP2_1
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select POSTCAR_STAGE
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select REG_SCRIPT
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select SMP
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select SOC_AHCI_PORT_IMPLEMENTED_INVERT
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@ -92,7 +92,6 @@ config USE_FSP2_0_DRIVER
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select PLATFORM_USES_FSP2_0
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select UDK_2015_BINDING
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select POSTCAR_STAGE
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config USE_FSP1_1_DRIVER
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def_bool y
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