mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs
Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed. Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -191,6 +191,7 @@ chip soc/intel/elkhartlake
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register "led_1_ctrl" = "1"
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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register "downshift_cnt" = "2"
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device mdio 0 on # PHY address
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ops m88e1512_ops
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end
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@ -206,6 +207,7 @@ chip soc/intel/elkhartlake
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register "led_1_ctrl" = "1"
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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register "downshift_cnt" = "2"
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device mdio 1 on # PHY address
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ops m88e1512_ops
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end
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@ -224,6 +226,7 @@ chip soc/intel/elkhartlake
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register "led_1_ctrl" = "1"
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# INTn is routed to LED[2] pin
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register "enable_int" = "true"
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register "downshift_cnt" = "2"
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device mdio 1 on # PHY address
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ops m88e1512_ops
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end
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