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src: Move constant to the right side of comparison 

Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2019-01-03 10:23:28 +01:00 committed by Patrick Georgi
parent f212cf3506
commit 0f8b8d920c
6 changed files with 9 additions and 9 deletions
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2
src/device/pci_class.c
View File

@ -263,7 +263,7 @@ const char *get_pci_subclass_name(struct device *dev)
subclass_name = "???";
class_entry = get_pci_class_entry(dev);
subclass_entry = class_entry ? class_entry->subclass_list : NULL;
if (NULL != subclass_entry) {
if (subclass_entry != NULL) {
subclass_list_end =
&subclass_entry[class_entry->subclass_entries];
while (subclass_list_end > subclass_entry) {

2
src/device/pci_rom.c
View File

@ -150,7 +150,7 @@ struct rom_header *pci_rom_load(struct device *dev,
* whether the ROM image is for a VGA device because some
* devices have a mismatch between the hardware and the ROM.
*/
if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) {
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
#if !IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; /* Primary VGA device (device.c). */
if (dev != vga_pri) return NULL; /* Only one VGA supported. */

2
src/northbridge/amd/agesa/family16kb/state_machine.c
View File

@ -34,7 +34,7 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
status = OemInitResume(&Post->MemConfig.MemContext);
if (AGESA_SUCCESS == status)
if (status == AGESA_SUCCESS)
Post->MemConfig.MemRestoreCtl = 1;
}
}

2
src/northbridge/amd/amdmct/mct/mctardk4.c
View File

@ -146,6 +146,6 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
}
}
p+=10;
} while (0xFF == *p);
} while (*p == 0xff);
}
}

6
src/southbridge/amd/cimx/sb800/late.c
View File

@ -353,9 +353,9 @@ static void sb800_enable(struct device *dev)
case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
if (sb_chip->boot_switch_sata_ide == 1)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
else if (sb_chip->boot_switch_sata_ide == 0)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
@ -387,7 +387,7 @@ static void sb800_enable(struct device *dev)
case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
if (sb_config->AzaliaController == AZALIA_DISABLE) {
sb_config->AzaliaController = AZALIA_AUTO;
}
} else {

4
src/southbridge/amd/cimx/sb900/late.c
View File

@ -354,9 +354,9 @@ static void sb900_enable(struct device *dev)
case (0x11 << 3) | 0: /* 0:11.0 SATA */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
if (sb_chip->boot_switch_sata_ide == 1)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
else if (sb_chip->boot_switch_sata_ide == 0)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SATAMODE.SataMode.SataController = DISABLED;