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fixed up tables. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2004-08-24 17:23:37 +00:00
parent 182615d635
commit 0fb38825cb
1 changed files with 19 additions and 21 deletions
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32
src/mainboard/densitron/dpx114/irq_tables.c
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@ -1,8 +1,8 @@
/* This file was generated by getpir.c, do not modify! /* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify) (but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
*
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/ */
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
@ -11,22 +11,20 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*5, /* there can be total 5 devices on the bus */ 32+16*5, /* there can be total 5 devices on the bus */
0, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
0x88, /* Where the interrupt router lies (dev) */ (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
0x1c20, /* IRQs devoted exclusively to PCI usage */ 0x1ea0, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */ 0, /* Vendor */
0x8231, /* Device */ 0, /* Device */
0, /* Crap (miniport) */ 0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 0x15, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
/* 8231 ethernet */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, {0x00,(0x09<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x1, 0x0},
/* 8231 internal */ {0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, {0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
/* PCI slot */ {0x00,(0x0f<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0}, {0x00,(0x02<<3)|0x0, {{0x59, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
} }
}; };