ChromeOS: Refactor SMBIOS type0 bios_version()
Pointer to an empty string (filled with spaces) is stored inside GNVS. Rearrange things to avoid having <chromeos/gnvs.h> in SMBIOS code. Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49281 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -2,6 +2,7 @@
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#include <acpi/acpi_gnvs.h>
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#include <acpi/acpi_gnvs.h>
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#include <ec/google/chromeec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <smbios.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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void gnvs_assign_chromeos(void)
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void gnvs_assign_chromeos(void)
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@ -27,3 +28,13 @@ void gnvs_set_ecfw_rw(void)
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gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
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gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
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}
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}
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void smbios_type0_bios_version(uintptr_t address)
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{
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chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
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if (!gnvs_chromeos)
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return;
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/* Location of smbios_type0.bios_version() string filled with spaces. */
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gnvs_chromeos->vbt10 = address;
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}
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@ -16,9 +16,6 @@
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#if CONFIG(CHROMEOS)
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#include <vendorcode/google/chromeos/gnvs.h>
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#endif
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#include <drivers/vpd/vpd.h>
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#include <drivers/vpd/vpd.h>
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#include <stdlib.h>
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#include <stdlib.h>
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@ -411,11 +408,12 @@ static int smbios_write_type0(unsigned long *current, int handle)
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t->vendor = smbios_add_string(t->eos, "coreboot");
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t->vendor = smbios_add_string(t->eos, "coreboot");
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t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
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t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
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#if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)
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if (CONFIG(CHROMEOS)) {
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u32 version_offset = (u32)smbios_string_table_len(t->eos);
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uintptr_t version_address = (uintptr_t)t->eos;
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/* SMBIOS offsets start at 1 rather than 0 */
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/* SMBIOS offsets start at 1 rather than 0 */
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chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1);
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version_address += (u32)smbios_string_table_len(t->eos) - 1;
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#endif
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smbios_type0_bios_version(version_address);
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}
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t->bios_version = smbios_add_string(t->eos, get_bios_version());
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t->bios_version = smbios_add_string(t->eos, get_bios_version());
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uint32_t rom_size = CONFIG_ROM_SIZE;
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uint32_t rom_size = CONFIG_ROM_SIZE;
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rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB);
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rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB);
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@ -55,6 +55,9 @@ const char *smbios_chassis_version(void);
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const char *smbios_chassis_serial_number(void);
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const char *smbios_chassis_serial_number(void);
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const char *smbios_processor_serial_number(void);
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const char *smbios_processor_serial_number(void);
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/* This string could be filled late in payload. */
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void smbios_type0_bios_version(uintptr_t address);
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void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision);
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void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision);
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unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo);
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unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo);
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