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nb/intel/ironlake: Use an enum for `gpu_panel_port_select` 

The PRM does not describe the relevant bits, but Linux's i915 driver
handles these bits the same way for both Ironlake and Sandy Bridge.

Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-09-02 19:24:59 +02:00 committed by Patrick Georgi
parent dc0c081001
commit 1057519074
4 changed files with 10 additions and 4 deletions
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2
src/mainboard/lenovo/t410/devicetree.cb
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@ -8,7 +8,7 @@ chip northbridge/intel/ironlake
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "1"
register "gpu_panel_power_up_delay" = "1"
register "gpu_panel_power_down_delay" = "600"

2
src/mainboard/lenovo/x201/devicetree.cb
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@ -9,7 +9,7 @@ chip northbridge/intel/ironlake
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "3"
register "gpu_panel_power_up_delay" = "250"
register "gpu_panel_power_down_delay" = "250"

2
src/mainboard/packardbell/ms2290/devicetree.cb
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@ -9,7 +9,7 @@ chip northbridge/intel/ironlake
register "gpu_dp_d_hotplug" = "0x04"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "6"
register "gpu_panel_power_up_delay" = "300"
register "gpu_panel_power_down_delay" = "300"

8
src/northbridge/intel/ironlake/chip.h
View File

@ -17,7 +17,13 @@ struct northbridge_intel_ironlake_config {
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
enum {
PANEL_PORT_LVDS = 0,
PANEL_PORT_DP_A = 1, /* Also known as eDP */
PANEL_PORT_DP_C = 2,
PANEL_PORT_DP_D = 3,
} gpu_panel_port_select;
u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
u16 gpu_panel_power_down_delay; /* T3 time sequence */