Various smaller fixes to make the ASUS P2B match the format
of all the other boards in this patch series. Add missing PIRQ table to make most devices work. Enable VGA support. Add flashrom flashing protection code. Make CPU init actually work (result: massive speed-up). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
68d8a56cc5
commit
113c2013bb
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@ -25,7 +25,8 @@ else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
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+ ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 64 * 1024
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@ -80,11 +81,16 @@ dir /pc80
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config chip.h
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # AGP bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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@ -99,11 +105,11 @@ chip northbridge/intel/i440bx # Northbridge
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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device pnp 3f0.5 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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@ -126,6 +132,4 @@ chip northbridge/intel/i440bx # Northbridge
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register "ide1_enable" = "1"
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end
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end
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chip cpu/intel/socket_PGA370
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end
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end
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@ -59,18 +59,27 @@ uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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default ROM_SIZE = 256 * 1024
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default HAVE_FALLBACK_BOOT = 1
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default HAVE_MP_TABLE = 0
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default HAVE_HARD_RESET = 0
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default HAVE_PIRQ_TABLE = 0
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default IRQ_SLOT_COUNT = 4
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
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default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
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default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
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default ROM_IMAGE_SIZE = 64 * 1024
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default FALLBACK_SIZE = 128 * 1024
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default STACK_SIZE = 8 * 1024
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default HEAP_SIZE = 16 * 1024
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default HAVE_OPTION_TABLE = 0
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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default STACK_SIZE = 0x2000
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default HEAP_SIZE = 0x4000
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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@ -81,9 +90,10 @@ default HOSTCC = "gcc"
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default TTYS0_BAUD = 115200
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default TTYS0_BASE = 0x3f8
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default TTYS0_LCS = 0x3
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default TTYS0_LCS = 0x3 # 8n1
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default DEFAULT_CONSOLE_LOGLEVEL = 9
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default MAXIMUM_CONSOLE_LOGLEVEL = 9
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_CONSOLE_VGA = 1
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default CONFIG_PCI_ROM_RUN = 1
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end
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@ -30,13 +30,13 @@
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
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#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
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#include "northbridge/intel/i440bx/raminit.h"
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#include "mainboard/bitworks/ims/debug.c" /* FIXME */
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#include "mainboard/asus/mew-vm/debug.c" /* FIXME */
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
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@ -64,10 +64,9 @@ static void main(unsigned long bist)
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w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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report_bist_failure(bist);
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enable_smbus();
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dump_spd_registers(&memctrl[0]);
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/* dump_spd_registers(&memctrl[0]); */
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sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
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ram_check(0, 640 * 1024);
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/* ram_check(0, 640 * 1024); */
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}
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@ -19,7 +19,4 @@
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*/
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extern struct chip_operations mainboard_asus_p2b_ops;
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struct mainboard_asus_p2b_config {
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int nothing;
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};
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struct mainboard_asus_p2b_config {};
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@ -0,0 +1,49 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x04 << 3) | 0x0, /* Interrupt router device */
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0, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x122e, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x54, /* Checksum */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
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{0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
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{0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
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{0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
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{0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
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{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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struct chip_operations mainboard_asus_p2b_ops = {
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CHIP_NAME("ASUS P2B Mainboard")
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};
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@ -23,16 +23,25 @@ mainboard asus/p2b
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option ROM_SIZE = 256 * 1024
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option MAINBOARD_VENDOR = "ASUS"
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option MAINBOARD_PART_NUMBER = "P2B"
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option IRQ_SLOT_COUNT = 6
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option DEFAULT_CONSOLE_LOGLEVEL = 9
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option MAXIMUM_CONSOLE_LOGLEVEL = 9
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option CONFIG_CONSOLE_VGA = 1
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option CONFIG_PCI_ROM_RUN = 1
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romimage "normal"
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option USE_FALLBACK_IMAGE = 0
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option ROM_IMAGE_SIZE = 64 * 1024
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option LINUXBIOS_EXTRA_VERSION = ".0Normal"
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payload /tmp/filo.elf
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end
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romimage "fallback"
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option USE_FALLBACK_IMAGE = 1
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option ROM_IMAGE_SIZE = 64 * 1024
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option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
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payload /tmp/filo.elf
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end
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