Various smaller fixes to make the ASUS P2B match the format

of all the other boards in this patch series.

Add missing PIRQ table to make most devices work.
Enable VGA support. Add flashrom flashing protection code.
Make CPU init actually work (result: massive speed-up).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/asus/p2b/Config.lb

@@ -25,7 +25,8 @@ else
 	default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
 	default ROM_SECTION_OFFSET = 0
 end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
+				    + ROM_SECTION_OFFSET + 1)
 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
 default XIP_ROM_SIZE = 64 * 1024
@@ -80,11 +81,16 @@ dir /pc80
 config chip.h
 
 chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# AGP bridge
+    device pci 1.0 on end		# PCI/AGP bridge
     chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA
+      device pci 4.0 on			# ISA bridge
         chip superio/winbond/w83977tf	# Super I/O
           device pnp 3f0.0 on		# Floppy
             io 0x60 = 0x3f0
@@ -99,11 +105,11 @@ chip northbridge/intel/i440bx		# Northbridge
             io 0x60 = 0x3f8
             irq 0x70 = 4
           end
-          device pnp 3f0.3 on		# COM2
+          device pnp 3f0.3 on		# COM2 / IR
             io 0x60 = 0x2f8
             irq 0x70 = 3
           end
-          device pnp 3f0.5 on		# PS/2 keyboard
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
             io 0x60 = 0x60
             io 0x62 = 0x64
             irq 0x70 = 1		# PS/2 keyboard interrupt
@@ -126,6 +132,4 @@ chip northbridge/intel/i440bx		# Northbridge
       register "ide1_enable" = "1"
     end
   end
-  chip cpu/intel/socket_PGA370
-  end
 end

src/mainboard/asus/p2b/Options.lb

@@ -59,18 +59,27 @@ uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
 uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
 
 default ROM_SIZE = 256 * 1024
 default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 0
+default CONFIG_UDELAY_TSC = 1
-default IRQ_SLOT_COUNT = 4
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
+default MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
 default HAVE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
-default STACK_SIZE = 0x2000
-default HEAP_SIZE = 0x4000
 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 default USE_OPTION_TABLE = 0
 default _RAMBASE = 0x00004000
@@ -81,9 +90,10 @@ default HOSTCC = "gcc"
 default CONFIG_CONSOLE_SERIAL8250 = 1
 default TTYS0_BAUD = 115200
 default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3
+default TTYS0_LCS = 0x3			# 8n1
 default DEFAULT_CONSOLE_LOGLEVEL = 9
 default MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_UDELAY_TSC = 1
+default CONFIG_CONSOLE_VGA = 1
+default CONFIG_PCI_ROM_RUN = 1
 
 end

src/mainboard/asus/p2b/auto.c

@@ -30,13 +30,13 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
-#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "mainboard/bitworks/ims/debug.c"		/* FIXME */
+#include "mainboard/asus/mew-vm/debug.c"	/* FIXME */
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
@@ -64,10 +64,9 @@ static void main(unsigned long bist)
 	w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
 	console_init();
-
 	report_bist_failure(bist);
 	enable_smbus();
-	dump_spd_registers(&memctrl[0]);
+	/* dump_spd_registers(&memctrl[0]); */
 	sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
-	ram_check(0, 640 * 1024);
+	/* ram_check(0, 640 * 1024); */
 }

src/mainboard/asus/p2b/chip.h

@@ -19,7 +19,4 @@
  */
 
 extern struct chip_operations mainboard_asus_p2b_ops;
-
+struct mainboard_asus_p2b_config {};
-struct mainboard_asus_p2b_config {
-	int nothing;
-};

src/mainboard/asus/p2b/irq_tables.c

@@ -0,0 +1,49 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x54,			/* Checksum */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
+		{0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
+		{0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
+		{0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
+		{0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

src/mainboard/asus/p2b/mainboard.c

@@ -24,4 +24,3 @@
 struct chip_operations mainboard_asus_p2b_ops = {
 	CHIP_NAME("ASUS P2B Mainboard")
 };
-

targets/asus/p2b/Config.lb

@@ -23,16 +23,25 @@ mainboard asus/p2b
 
 option ROM_SIZE = 256 * 1024
 
+option MAINBOARD_VENDOR = "ASUS"
+option MAINBOARD_PART_NUMBER = "P2B"
+
+option IRQ_SLOT_COUNT = 6
+
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+option CONFIG_CONSOLE_VGA = 1
+option CONFIG_PCI_ROM_RUN = 1
+
 romimage "normal"
 	option USE_FALLBACK_IMAGE = 0
-	option ROM_IMAGE_SIZE = 64 * 1024
 	option LINUXBIOS_EXTRA_VERSION = ".0Normal"
 	payload /tmp/filo.elf
 end
 
 romimage "fallback"
 	option USE_FALLBACK_IMAGE = 1
-	option ROM_IMAGE_SIZE = 64 * 1024
 	option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
 	payload /tmp/filo.elf
 end