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arm64: remove spin table support 

As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove spintable
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.

Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11908
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Aaron Durbin 2015-10-15 12:22:27 -05:00 committed by Julius Werner
parent 0325a45fd0
commit 1148786c05
17 changed files with 0 additions and 214 deletions
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5
src/arch/arm64/Kconfig
View File

@ -28,11 +28,6 @@ config ARM64_BOOTBLOCK_CUSTOM
bool
default n
config ARM64_USE_SPINTABLE
bool
default n
depends on ARCH_RAMSTAGE_ARM64
config ARM64_USE_ARM_TRUSTED_FIRMWARE
bool
default n

1
src/arch/arm64/Makefile.inc
View File

@ -142,7 +142,6 @@ ramstage-y += memcpy.S
ramstage-y += memmove.S
ramstage-y += stage_entry.S
ramstage-y += cpu-stubs.c
ramstage-$(CONFIG_ARM64_USE_SPINTABLE) += spintable.c spintable_asm.S
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c
ramstage-y += transition.c transition_asm.S

5
src/arch/arm64/boot.c
View File

@ -16,7 +16,6 @@
#include <arch/cache.h>
#include <arch/lib_helpers.h>
#include <arch/stages.h>
#include <arch/spintable.h>
#include <arch/transition.h>
#include <arm_tf.h>
#include <cbmem.h>
@ -39,10 +38,6 @@ static void run_payload(struct prog *prog)
else {
uint8_t current_el = get_current_el();
/* Start the other CPUs spinning. */
if (IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE))
spintable_start();
cache_sync_instructions();
printk(BIOS_SPEW, "entry = %p\n", doit);

45
src/arch/arm64/include/arch/spintable.h
View File

@ -1,45 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_SPINTABLE_H__
#define __ARCH_SPINTABLE_H__
struct spintable_attributes {
void (*entry)(void *);
void *addr;
};
#if IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE)
/* Initialize spintable with provided monitor address. */
void spintable_init(void *monitor_address);
/* Return NULL on failure, otherwise the spintable info. */
const struct spintable_attributes *spintable_get_attributes(void);
#else /* IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) */
static inline void spintable_init(void *monitor_address) {}
static inline const struct spintable_attributes *spintable_get_attributes(void)
{
return NULL;
}
#endif /* IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) */
/* Start spinning on the non-boot CPUs. */
void spintable_start(void);
#endif /* __ARCH_SPINTABLE_H__ */

96
src/arch/arm64/spintable.c
View File

@ -1,96 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cache.h>
#include <arch/spintable.h>
#include <arch/transition.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include <string.h>
static struct spintable_attributes spin_attrs;
void spintable_init(void *monitor_address)
{
extern void __wait_for_spin_table_request(void);
const size_t code_size = 4096;
if (monitor_address == NULL) {
printk(BIOS_ERR, "spintable: NULL address to monitor.\n");
return;
}
spin_attrs.entry = cbmem_add(CBMEM_ID_SPINTABLE, code_size);
if (spin_attrs.entry == NULL)
return;
spin_attrs.addr = monitor_address;
printk(BIOS_INFO, "spintable @ %p will monitor %p\n",
spin_attrs.entry, spin_attrs.addr);
/* Ensure the memory location is zero'd out. */
*(uint64_t *)monitor_address = 0;
memcpy(spin_attrs.entry, __wait_for_spin_table_request, code_size);
dcache_clean_invalidate_by_mva(monitor_address, sizeof(uint64_t));
dcache_clean_invalidate_by_mva(spin_attrs.entry, code_size);
}
static void spintable_enter(void *unused)
{
struct exc_state state;
const struct spintable_attributes *attrs;
int current_el;
attrs = spintable_get_attributes();
current_el = get_current_el();
if (current_el != EL3)
attrs->entry(attrs->addr);
memset(&state, 0, sizeof(state));
state.elx.spsr = get_eret_el(EL2, SPSR_USE_L);
transition_with_entry(attrs->entry, attrs->addr, &state);
}
const struct spintable_attributes *spintable_get_attributes(void)
{
if (spin_attrs.entry == NULL) {
printk(BIOS_ERR, "spintable: monitor code not present.\n");
return NULL;
}
return &spin_attrs;
}
void spintable_start(void)
{
struct cpu_action action = {
.run = spintable_enter,
};
if (spintable_get_attributes() == NULL)
return;
printk(BIOS_INFO, "All non-boot CPUs to enter spintable.\n");
arch_run_on_all_cpus_but_self_async(&action);
}

34
src/arch/arm64/spintable_asm.S
View File

@ -1,34 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/asm.h>
ENTRY(__wait_for_spin_table_request)
/* Entry here is in EL2 with the magic address in x0. */
mov x28, x0
1:
ldr x27, [x28]
cmp x27, xzr
b.ne 2f
wfe
b 1b
2:
/* Entry into the kernel. */
mov x0, xzr
mov x1, xzr
mov x2, xzr
mov x3, xzr
br x27
ENDPROC(__wait_for_spin_table_request)

2
src/commonlib/include/commonlib/cbmem_id.h
View File

@ -55,7 +55,6 @@
#define CBMEM_ID_ROOT 0xff4007ff
#define CBMEM_ID_SMBIOS 0x534d4254
#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
#define CBMEM_ID_SPINTABLE 0x59175917
#define CBMEM_ID_STAGEx_META 0x57a9e000
#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
#define CBMEM_ID_TCPA_LOG 0x54435041
@ -101,7 +100,6 @@
{ CBMEM_ID_ROOT, "CBMEM ROOT " }, \
{ CBMEM_ID_SMBIOS, "SMBIOS " }, \
{ CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
{ CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
{ CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
{ CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
{ CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \

2
src/mainboard/google/foster/devicetree.cb
View File

@ -14,8 +14,6 @@
##
chip soc/nvidia/tegra210
register "spintable_addr" = "0x80000008"
device cpu_cluster 0 on
device cpu 0 on end
device cpu 1 on end

1
src/mainboard/google/rush/Kconfig
View File

@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_SOR_INIT
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_4096
select ARM64_USE_SPINTABLE
config CHROMEOS
select CHROMEOS_VBNV_EC

2
src/mainboard/google/rush/devicetree.cb
View File

@ -14,8 +14,6 @@
##
chip soc/nvidia/tegra132
register "spintable_addr" = "0x80000008"
device cpu_cluster 0 on
device cpu 0 on end
device cpu 1 on end

1
src/mainboard/google/rush_ryu/Kconfig
View File

@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_DSI_INIT
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_8192
select ARM64_USE_SPINTABLE
config CHROMEOS
select CHROMEOS_VBNV_EC

2
src/mainboard/google/rush_ryu/devicetree.cb
View File

@ -14,8 +14,6 @@
##
chip soc/nvidia/tegra132
register "spintable_addr" = "0x80000008"
device cpu_cluster 0 on
device cpu 0 on end
device cpu 1 on end

2
src/mainboard/google/smaug/devicetree.cb
View File

@ -14,8 +14,6 @@
##
chip soc/nvidia/tegra210
register "spintable_addr" = "0x80000008"
device cpu_cluster 0 on
device cpu 0 on end
end

3
src/soc/nvidia/tegra132/chip.h
View File

@ -20,9 +20,6 @@
#include <soc/nvidia/tegra/dc.h>
struct soc_nvidia_tegra132_config {
/* Address to monitor if spintable employed. */
uintptr_t spintable_addr;
/*
* panel resolution
* The two parameters below provides dc about panel spec.

5
src/soc/nvidia/tegra132/soc.c
View File

@ -16,7 +16,6 @@
#include <arch/io.h>
#include <arch/cache.h>
#include <arch/spintable.h>
#include <cpu/cpu.h>
#include <bootmode.h>
#include <bootstate.h>
@ -86,12 +85,8 @@ static void lock_down_vpr(void)
static void soc_init(device_t dev)
{
struct soc_nvidia_tegra132_config *cfg;
clock_init_arm_generic_timer();
cfg = dev->chip_info;
spintable_init((void *)cfg->spintable_addr);
arch_initialize_cpus(dev, &cntrl_ops);
/* Lock down VPR */

3
src/soc/nvidia/tegra210/chip.h
View File

@ -20,9 +20,6 @@
#include <soc/nvidia/tegra/dc.h>
struct soc_nvidia_tegra210_config {
/* Address to monitor if spintable employed. */
uintptr_t spintable_addr;
/*
* panel resolution
* The two parameters below provides dc about panel spec.

5
src/soc/nvidia/tegra210/soc.c
View File

@ -16,7 +16,6 @@
#include <arch/io.h>
#include <arch/cache.h>
#include <arch/spintable.h>
#include <cpu/cpu.h>
#include <bootmode.h>
#include <bootstate.h>
@ -80,12 +79,8 @@ static struct cpu_control_ops cntrl_ops = {
static void soc_init(device_t dev)
{
struct soc_nvidia_tegra210_config *cfg;
clock_init_arm_generic_timer();
cfg = dev->chip_info;
spintable_init((void *)cfg->spintable_addr);
arch_initialize_cpus(dev, &cntrl_ops);
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))