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Drop invalid device ops on Agesa northbridge 

One could not pass a device of type APIC to PCI resource functions.
The correct CPU model specific cpu->ops is set at later time in
cpu_initialize().

Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki 2012-07-06 17:27:37 +03:00 committed by Patrick Georgi
parent de3dde46fd
commit 1171986627
3 changed files with 0 additions and 54 deletions
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18
src/northbridge/amd/agesa/family10/northbridge.c
View File

@ -1210,21 +1210,6 @@ static void add_more_links(device_t dev, unsigned total_links)
last->next = NULL; last->next = NULL;
} }
/* dummy read_resources */
static void lapic_read_resources(device_t dev)
{
}
static struct device_operations lapic_ops = {
.read_resources = lapic_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.enable = 0,
.ops_pci = 0,
};
static u32 cpu_bus_scan(device_t dev, u32 max) static u32 cpu_bus_scan(device_t dev, u32 max)
{ {
struct bus *cpu_bus; struct bus *cpu_bus;
@ -1426,9 +1411,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (cpu) { if (cpu) {
cpu->path.apic.node_id = i; cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j; cpu->path.apic.core_id = j;
if (cpu->path.type == DEVICE_PATH_APIC) {
cpu->ops = &lapic_ops;
}
printk(BIOS_DEBUG, "CPU: %s %s\n", printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled"); dev_path(cpu), cpu->enabled?"enabled":"disabled");
} }

18
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -916,21 +916,6 @@ static void add_more_links(device_t dev, unsigned total_links)
last->next = NULL; last->next = NULL;
} }
/* dummy read_resources */
static void lapic_read_resources(device_t dev)
{
}
static struct device_operations lapic_ops = {
.read_resources = lapic_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.enable = 0,
.ops_pci = 0,
};
static u32 cpu_bus_scan(device_t dev, u32 max) static u32 cpu_bus_scan(device_t dev, u32 max)
{ {
struct bus *cpu_bus; struct bus *cpu_bus;
@ -1127,9 +1112,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (cpu) { if (cpu) {
cpu->path.apic.node_id = i; cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j; cpu->path.apic.core_id = j;
if (cpu->path.type == DEVICE_PATH_APIC) {
cpu->ops = &lapic_ops;
}
printk(BIOS_DEBUG, "CPU: %s %s\n", printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled"); dev_path(cpu), cpu->enabled?"enabled":"disabled");
} }

18
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -852,21 +852,6 @@ static void add_more_links(device_t dev, unsigned total_links)
last->next = NULL; last->next = NULL;
} }
/* dummy read_resources */
static void lapic_read_resources(device_t dev)
{
}
static struct device_operations lapic_ops = {
.read_resources = lapic_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.enable = 0,
.ops_pci = 0,
};
static u32 cpu_bus_scan(device_t dev, u32 max) static u32 cpu_bus_scan(device_t dev, u32 max)
{ {
struct bus *cpu_bus; struct bus *cpu_bus;
@ -1063,9 +1048,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (cpu) { if (cpu) {
cpu->path.apic.node_id = i; cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j; cpu->path.apic.core_id = j;
if (cpu->path.type == DEVICE_PATH_APIC) {
cpu->ops = &lapic_ops;
}
printk(BIOS_DEBUG, "CPU: %s %s\n", printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled"); dev_path(cpu), cpu->enabled?"enabled":"disabled");
} }