make solo target build again
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
57ffeb0578
commit
1188bd2adc
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@ -1,19 +1,30 @@
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#define ASSEMBLY 1
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#define MAXIMUM_CONSOLE_LOGLEVEL 9
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#define DEFAULT_CONSOLE_LOGLEVEL 9
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#include <stdint.h>
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#include <device/pci_def.h>
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#include "arch/romcc_io.h"
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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static void memreset_setup(const struct mem_controller *ctrl)
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static void memreset_setup(void)
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{
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}
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static void memreset(const struct mem_controller *ctrl)
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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@ -22,7 +33,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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/* since the AMD Solo is a UP only machine, we can
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* always return the default row entry value
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*/
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return 0x00010101; /* default row entry */
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return 0x00010101; /* default row entry */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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@ -30,215 +41,95 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#define NODE_ID 0x60
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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static int boot_cpu(void)
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static void enable_lapic(void)
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{
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volatile unsigned long *local_apic;
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unsigned long apic_id;
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int bsp;
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msr_t msr;
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msr = rdmsr(0x1b);
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bsp = !!(msr.lo & (1 << 8));
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if (bsp) {
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print_debug("Bootstrap processor\r\n");
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} else {
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print_debug("Application processor\r\n");
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}
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return bsp;
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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}
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static int cpu_init_detected(void)
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static void stop_this_cpu(void)
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{
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unsigned long dcl;
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int cpu_init;
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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unsigned long htic;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
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#if 0
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print_debug("htic: ");
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print_debug_hex32(htic);
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print_debug("\r\n");
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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if (!(htic & HTIC_ColdR_Detect)) {
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print_debug("Cold Reset.\r\n");
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}
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if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
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print_debug("BIOS generated Reset.\r\n");
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}
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if (htic & HTIC_INIT_Detect) {
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print_debug("Init event.\r\n");
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}
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#endif
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cpu_init = (htic & HTIC_INIT_Detect);
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if (cpu_init) {
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print_debug("CPU INIT Detected.\r\n");
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}
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return cpu_init;
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}
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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/* If I haven't halted spin forever */
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for(;;) {
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hlt();
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".1: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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}
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}
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static void main(void)
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{
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static const struct mem_controller cpu0 = {
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa << 3), (0xa << 3)|1, 0, 0 },
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.channel1 = { 0, 0, 0, 0},
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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*/
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static const struct mem_controller cpu[] = {
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3), (0xa<<3)|1, 0, 0 },
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.channel1 = { 0, 0, 0, 0 },
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}
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};
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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enable_lapic();
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init_timer();
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if (!boot_cpu()) {
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notify_bsp_ap_is_stopped();
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stop_this_cpu();
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}
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uart_init();
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console_init();
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#if 0
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print_debug(" XIP_ROM_BASE: ");
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print_debug_hex32(XIP_ROM_BASE);
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print_debug(" XIP_ROM_SIZE: ");
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print_debug_hex32(XIP_ROM_SIZE);
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print_debug("\r\n");
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#endif
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if (boot_cpu() && !cpu_init_detected()) {
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain();
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print_pci_devices();
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enable_smbus();
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dump_spd_registers(&cpu0);
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sdram_initialize(&cpu0);
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain(0);
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distinguish_cpu_resets(0);
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enable_smbus();
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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/* Check the first 512M */
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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ram_check(0x00000000, msr.lo);
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}
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memreset_setup();
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sdram_initialize(1, cpu);
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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ram_check(0x00000000, msr.lo);
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}
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@ -2,22 +2,37 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "arch/romcc_io.h"
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#include "pc80/mc146818rtc_early.c"
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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static void main(void)
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{
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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enumerate_ht_chain(0);
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/* Setup the 8111 */
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amd8111_enable_rom();
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if (do_normal_boot()) {
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/* Jump to the normal image */
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/* Is this a cpu reset? */
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if (cpu_init_detected()) {
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if (last_boot_normal()) {
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asm("jmp __normal_image");
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} else {
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asm("jmp __cpu_reset");
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}
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}
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/* Is this a secondary cpu? */
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else if (!boot_cpu() && last_boot_normal()) {
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asm("jmp __normal_image");
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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asm("jmp __normal_image");
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}
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}
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