AGESA: Remove Kconfig AMD_AGESA_FAMILY10
Never selected in our tree. The vendorcode source for fam15 also includes fam10 support if required. Change-Id: Ifff328ecdd8afa988f844b6fd631818b51bd5b5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki
parent
8e0bc131c8
commit
1203115077
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@ -15,7 +15,6 @@
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config CPU_AMD_AGESA
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bool
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default y if CPU_AMD_AGESA_FAMILY10
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default y if CPU_AMD_AGESA_FAMILY12
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY15
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@ -82,7 +81,6 @@ config S3_DATA_SIZE
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endif # CPU_AMD_AGESA
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source src/cpu/amd/agesa/family10/Kconfig
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source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family15/Kconfig
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@ -12,7 +12,6 @@
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
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@ -1,43 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config CPU_AMD_AGESA_FAMILY10
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bool
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select CPU_AMD_MODEL_10XXX
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_AGESA_FAMILY10
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config CBB
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hex
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default 0x0
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config CDB
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hex
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default 0x18
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config XIP_ROM_SIZE
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hex
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default 0x80000
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config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
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bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
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default n
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help
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This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
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Warning: Only enable this option when debuging or tracing AMD AGESA code.
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endif #CPU_AMD_AGESA_FAMILY10
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@ -1,26 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ramstage-y += chip_name.c
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ramstage-y += model_10_init.c
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subdirs-y += ../../mtrr
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subdirs-y += ../../../x86/tsc
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subdirs-y += ../../../x86/lapic
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subdirs-y += ../../../x86/cache
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subdirs-y += ../../../x86/mtrr
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subdirs-y += ../../../x86/pae
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subdirs-y += ../../../x86/smm
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@ -1,20 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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struct chip_operations cpu_amd_agesa_family10_ops = {
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CHIP_NAME("AMD CPU Family 10h")
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};
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@ -1,107 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <string.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/pae.h>
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#include <pc80/mc146818rtc.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include "northbridge/amd/agesa/family10/amdfam10.h"
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#define MCI_STATUS 0x401
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static void model_10_init(device_t dev)
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{
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printk(BIOS_DEBUG, "Model 10 Init.\n");
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u8 i;
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msr_t msr;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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#endif
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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amd_setup_mtrrs();
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x86_mtrr_check();
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disable_cache();
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++) {
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wrmsr(MCI_STATUS + (i * 4), msr);
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}
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enable_cache();
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/* Enable the local CPU APICs */
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setup_lapic();
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/* Set the processor name string */
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// init_processor_name();
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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siblings = cpuid_ecx(0x80000008) & 0xff;
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr.lo |= 1 << 28;
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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#endif
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/* DisableCf8ExtCfg */
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msr = rdmsr(NB_CFG_MSR);
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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/* Write protect SMM space with SMMLOCK. */
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msr = rdmsr(HWCR_MSR);
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msr.lo |= (1 << 0);
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wrmsr(HWCR_MSR, msr);
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_10_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */
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{ X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */
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{ X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */
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{ X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */
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{ 0, 0 },
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};
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static const struct cpu_driver model_10 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -15,7 +15,6 @@
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ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y)
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
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@ -1,40 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Advanced Micro Devices, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_AMD_AGESA_FAMILY10
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bool
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select HAVE_DEBUG_RAM_SETUP
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select HAVE_DEBUG_SMBUS
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select HYPERTRANSPORT_PLUGIN_SUPPORT
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if NORTHBRIDGE_AMD_AGESA_FAMILY10
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config MMCONF_BASE_ADDRESS
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hex
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default 0xE0000000
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config MMCONF_BUS_NUMBER
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int
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default 256
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endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
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@ -1,16 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ramstage-y += northbridge.c
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