GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA: Remove Kconfig AMD_AGESA_FAMILY10 

Never selected in our tree. The vendorcode source
for fam15 also includes fam10 support if required.

Change-Id: Ifff328ecdd8afa988f844b6fd631818b51bd5b5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2017-08-24 10:27:59 +03:00
parent 8e0bc131c8
commit 1203115077
10 changed files with 0 additions and 1395 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/agesa/Kconfig
View File

@ -15,7 +15,6 @@
config CPU_AMD_AGESA config CPU_AMD_AGESA
bool bool
default y if CPU_AMD_AGESA_FAMILY10
default y if CPU_AMD_AGESA_FAMILY12 default y if CPU_AMD_AGESA_FAMILY12
default y if CPU_AMD_AGESA_FAMILY14 default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15 default y if CPU_AMD_AGESA_FAMILY15
@ -82,7 +81,6 @@ config S3_DATA_SIZE
endif # CPU_AMD_AGESA endif # CPU_AMD_AGESA
source src/cpu/amd/agesa/family10/Kconfig
source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family12/Kconfig
source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig source src/cpu/amd/agesa/family15/Kconfig

1
src/cpu/amd/agesa/Makefile.inc
View File

@ -12,7 +12,6 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details. # GNU General Public License for more details.
# #
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15

43
src/cpu/amd/agesa/family10/Kconfig
View File

@ -1,43 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
config CPU_AMD_AGESA_FAMILY10
bool
select CPU_AMD_MODEL_10XXX
select X86_AMD_FIXED_MTRRS
if CPU_AMD_AGESA_FAMILY10
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000
config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
default n
help
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
Warning: Only enable this option when debuging or tracing AMD AGESA code.
endif #CPU_AMD_AGESA_FAMILY10

26
src/cpu/amd/agesa/family10/Makefile.inc
View File

@ -1,26 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ramstage-y += chip_name.c
ramstage-y += model_10_init.c
subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm

20
src/cpu/amd/agesa/family10/chip_name.c
View File

@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
struct chip_operations cpu_amd_agesa_family10_ops = {
CHIP_NAME("AMD CPU Family 10h")
};

107
src/cpu/amd/agesa/family10/model_10_init.c
View File

@ -1,107 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include "northbridge/amd/agesa/family10/amdfam10.h"
#define MCI_STATUS 0x401
static void model_10_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 10 Init.\n");
u8 i;
msr_t msr;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
disable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
enable_cache();
/* Enable the local CPU APICs */
setup_lapic();
/* Set the processor name string */
// init_processor_name();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static struct device_operations cpu_dev_ops = {
.init = model_10_init,
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */
{ X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */
{ X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */
{ X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */
{ 0, 0 },
};
static const struct cpu_driver model_10 __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

1
src/northbridge/amd/agesa/Makefile.inc
View File

@ -15,7 +15,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y)
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15

40
src/northbridge/amd/agesa/family10/Kconfig
View File

@ -1,40 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_AMD_AGESA_FAMILY10
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
select HYPERTRANSPORT_PLUGIN_SUPPORT
if NORTHBRIDGE_AMD_AGESA_FAMILY10
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config MMCONF_BASE_ADDRESS
hex
default 0xE0000000
config MMCONF_BUS_NUMBER
int
default 256
endif #NORTHBRIDGE_AMD_AGESA_FAMILY10

16
src/northbridge/amd/agesa/family10/Makefile.inc
View File

@ -1,16 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ramstage-y += northbridge.c

1139
src/northbridge/amd/agesa/family10/northbridge.c
View File

File diff suppressed because it is too large Load Diff