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soc/intel/alderlake/Kconfig: Sort defaults alphabetically 

"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions

Swap the position of two lines so that defaults are listed in
alphabetical order according to the PCH type: M, N, P, S.

Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Angel Pons 2022-12-09 12:32:12 +01:00 committed by Eric Lai
parent 5a724a1adc
commit 122e1dfe5d
1 changed files with 1 additions and 1 deletions
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src/soc/intel/alderlake/Kconfig
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@ -252,8 +252,8 @@ config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
help
With external clock buffer, Alderlake-P can support up to three additional source clocks.
This is done by setting the corresponding GPIO pin(s) to native function to use as