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mb/google/hatch: Enable CNVi Wifi for hatch 

This patch enables CNVi wifi for hatch
1. Enable CNVi device in device tree
2. Configure GPIO pad config for CNVi

BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics

Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30436
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela 2018-12-26 17:26:47 +05:30 committed by Subrata Banik
parent a9fadb007d
commit 126c27da06
2 changed files with 10 additions and 0 deletions
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4
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -154,6 +154,10 @@ chip soc/intel/cannonlake
end
end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
chip drivers/intel/wifi
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi wifi
end
device pci 14.5 off end # SDCard
device pci 15.0 on
chip drivers/i2c/generic

6
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -71,6 +71,12 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_E20, DN_20K),
/* DDPD_CTRLCLK => NC */
PAD_NC(GPP_E22, DN_20K),
/* GPIO_WWAN_WLAN_COEX3 */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
/* UART_WWANTX_WLANRX_COEX1 */
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
/* UART_WWANRX_WLANTX_COEX2 */
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
/* PCH_MEM_STRAP0 */
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
/* PCH_MEM_STRAP1 */